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SH7011
Hardware Manual
ADE-602-169 Rev. 1.0 3/4/03 Hitachi, Ltd.
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Contents
Section 1
1.1 1.2 1.3
SH7011 Overview .......................................................................................... SH7011 Overview ............................................................................................................. 1.1.1 SH7011 Features .................................................................................................. Block Diagram................................................................................................................... Pin Arrangement and Pin Functions.................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions........................................................................................................ CPU.....................................................................................................................
1 1 1 4 5 5 6 9 9 9 10 11 11 12 12 12 12 13 13 16 20 23 36 36
Section 2
2.1
2.2
2.3
2.4 2.5
Register Configuration ...................................................................................................... 2.1.1 General Registers (Rn) ......................................................................................... 2.1.2 Control Registers.................................................................................................. 2.1.3 System Registers .................................................................................................. 2.1.4 Initial Values of Registers .................................................................................... Data Formats...................................................................................................................... 2.2.1 Data Format in Registers...................................................................................... 2.2.2 Data Format in Memory ....................................................................................... 2.2.3 Immediate Data Format........................................................................................ Instruction Features............................................................................................................ 2.3.1 RISC-Type Instruction Set ................................................................................... 2.3.2 Addressing Modes................................................................................................ 2.3.3 Instruction Format ................................................................................................ Instruction Set by Classification........................................................................................ Processing States ............................................................................................................... 2.5.1 State Transitions ...................................................................................................
Section 3
3.1 3.2
Power-Down State.......................................................................................... 39
39 39 40 40 40
Overview............................................................................................................................ 3.1.1 Power-Down State................................................................................................ Sleep Mode........................................................................................................................ 3.2.1 Transition to Sleep Mode ..................................................................................... 3.2.2 Exit from Sleep Mode ..........................................................................................
Section 4
4.1 4.2
4.3
Clock Pulse Generator (CPG)..................................................................... 41 Overview............................................................................................................................ 41 Clock Source...................................................................................................................... 41 4.2.1 Crystal Resonator Connection.............................................................................. 41 4.2.2 External Clock Input ............................................................................................ 43 Usage Notes ....................................................................................................................... 43
i
Section 5
5.1
5.2
5.3 5.4
5.5
5.6
5.7 5.8
Exception Processing .................................................................................... Overview............................................................................................................................ 5.1.1 Types of Exception Processing and Priority ........................................................ 5.1.2 Exception Processing Operations ......................................................................... 5.1.3 Exception Processing Vector Table...................................................................... Resets................................................................................................................................. 5.2.1 Reset ..................................................................................................................... 5.2.2 Power-On Reset.................................................................................................... Address Errors ................................................................................................................... 5.3.1 Address Error Exception Processing.................................................................... Interrupts............................................................................................................................ 5.4.1 Interrupt Priority Level......................................................................................... 5.4.2 Interrupt Exception Processing ............................................................................ Exceptions Triggered by Instructions................................................................................ 5.5.1 Trap Instructions .................................................................................................. 5.5.2 Illegal Slot Instructions ........................................................................................ 5.5.3 General Illegal Instructions .................................................................................. When Exception Sources Are Not Accepted..................................................................... 5.6.1 Immediately after a Delayed Branch Instruction.................................................. 5.6.2 Immediately after an Interrupt-Disabled Instruction............................................ Stack Status after Exception Processing Ends................................................................... Notes on Use...................................................................................................................... 5.8.1 Value of Stack Pointer (SP).................................................................................. 5.8.2 Value of Vector Base Register (VBR) ................................................................. 5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing......
Overview............................................................................................................................ 6.1.1 Features ................................................................................................................ 6.1.2 Block Diagram...................................................................................................... 6.1.3 Pin Configuration ................................................................................................. 6.1.4 Register Configuration ......................................................................................... Interrupt Sources................................................................................................................ 6.2.1 NMI Interrupts...................................................................................................... 6.2.2 IRQ Interrupts ...................................................................................................... 6.2.3 On-Chip Peripheral Module Interrupts ................................................................ 6.2.4 Interrupt Exception Vectors and Priority Rankings ............................................. Description of Registers .................................................................................................... 6.3.1 Interrupt Priority Registers A-H (IPRA-IPRH) .................................................. 6.3.2 Interrupt Control Register (ICR) .......................................................................... 6.3.3 IRQ Status Register (ISR) .................................................................................... Interrupt Operation ............................................................................................................ 6.4.1 Interrupt Sequence................................................................................................
45 45 45 46 47 49 49 49 50 50 51 51 52 52 53 53 53 54 54 54 55 56 56 56 56
Section 6
6.1
Interrupt Controller (INTC)......................................................................... 57
57 57 58 59 59 60 60 60 61 61 64 64 65 66 68 68
6.2
6.3
6.4
ii
6.5
6.4.2 Stack after Interrupt Exception Processing .......................................................... 70 Interrupt Response Time.................................................................................................... 70
Section 7
7.1
7.2
7.3
7.4
7.5
Bus State Controller (BSC) ......................................................................... Overview............................................................................................................................ 7.1.1 Features ................................................................................................................ 7.1.2 Block Diagram...................................................................................................... 7.1.3 Pin Configuration ................................................................................................. 7.1.4 Register Configuration ......................................................................................... 7.1.5 Address Map ........................................................................................................ Description of Registers .................................................................................................... 7.2.1 Bus Control Register 2 (BCR2)............................................................................ 7.2.2 Wait Control Register 1 (WCR1) ......................................................................... Accessing Ordinary Space................................................................................................. 7.3.1 Basic Timing ........................................................................................................ 7.3.2 Wait State Control................................................................................................ 7.3.3 CS Assert Period Extension.................................................................................. Waits between Access Cycles ........................................................................................... 7.4.1 Prevention of Data Bus Conflicts ......................................................................... 7.4.2 Simplification of Bus Cycle Start Detection ........................................................ Memory Connection Examples .........................................................................................
Overview............................................................................................................................ 8.1.1 Features ................................................................................................................ 8.1.2 Block Diagram...................................................................................................... 8.1.3 Pin Configuration ................................................................................................. 8.1.4 Register Configuration ......................................................................................... MTU Register Descriptions............................................................................................... 8.2.1 Timer Control Register (TCR) ............................................................................. 8.2.2 Timer Mode Register (TMDR) ............................................................................ 8.2.3 Timer I/O Control Register (TIOR) ..................................................................... 8.2.4 Timer Interrupt Enable Register (TIER) .............................................................. 8.2.5 Timer Status Register (TSR) ................................................................................ 8.2.6 Timer Counters (TCNT)....................................................................................... 8.2.7 Timer General Register (TGR) ............................................................................ 8.2.8 Timer Start Register (TSTR)................................................................................ 8.2.9 Timer Synchro Register (TSYR).......................................................................... Bus Master Interface.......................................................................................................... 8.3.1 16-Bit Registers.................................................................................................... 8.3.2 8-Bit Registers...................................................................................................... Operation ........................................................................................................................... 8.4.1 Overview ..............................................................................................................
73 73 73 74 75 75 76 77 77 80 82 82 83 85 86 86 87 88
Section 8
8.1
Multifunction Timer Pulse Unit (MTU).................................................. 89
89 89 92 93 94 95 95 99 100 107 109 111 112 112 113 114 114 114 116 116
iii
8.2
8.3
8.4
8.5
8.6
8.7 8.8
8.4.2 Basic Functions .................................................................................................... 8.4.3 Synchronous Operation ........................................................................................ 8.4.4 Buffer Operation .................................................................................................. 8.4.5 Cascade Connection Mode ................................................................................... 8.4.6 PWM Mode .......................................................................................................... Interrupts............................................................................................................................ 8.5.1 Interrupt Sources and Priority Ranking................................................................ 8.5.2 A/D Converter Activation .................................................................................... Operation Timing .............................................................................................................. 8.6.1 Input/Output Timing ............................................................................................ 8.6.2 Interrupt Signal Timing........................................................................................ Notes and Precautions........................................................................................................ MTU Output Pin Initialization .......................................................................................... 8.8.1 Operating Modes .................................................................................................. 8.8.2 Reset Start Operation............................................................................................ 8.8.3 Operation in Case of Re-Setting Due to Error During Operation, Etc................. 8.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error During Operation, Etc. .........................................................................................
116 122 124 127 128 133 133 134 135 135 139 141 150 150 151 151 152
Section 9
9.1
8-Bit Timer 1 (TIM1).................................................................................... 163
163 163 164 165 165 165 166 167 168 168 169 170 170 170
9.2
9.3
9.4
Overview............................................................................................................................ 9.1.1 Features ................................................................................................................ 9.1.2 Block Diagram...................................................................................................... 9.1.3 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 9.2.1 Timer 1 Counter (T1CNT) ................................................................................... 9.2.2 Timer 1 Control/Status Register (T1CSR) ........................................................... 9.2.3 Notes on Register Access ..................................................................................... Operation ........................................................................................................................... 9.3.1 Interval Timer Operation...................................................................................... 9.3.2 Timing of Overflow Flag (OVF) Setting.............................................................. Usage Notes ....................................................................................................................... 9.4.1 Contention between Timer 1 Counter (TCNT) Write and Increment.................. 9.4.2 Rewriting Bits CKS2 to CKS0 .............................................................................
Section 10 8-Bit Timer 2 (TIM2).................................................................................... 171
10.1 Overview............................................................................................................................ 10.1.1 Features ................................................................................................................ 10.1.2 Block Diagram...................................................................................................... 10.1.3 Register Configuration ......................................................................................... 10.2 Register Descriptions......................................................................................................... 10.2.1 Timer 2 Control/Status Register (T2CSR) ........................................................... 10.2.2 Timer 2 Counter (T2CNT) ...................................................................................
iv
171 171 172 172 173 173 174
10.2.3 Timer 2 Constant Register (T2COR) ................................................................... 10.3 Operation ........................................................................................................................... 10.3.1 Cyclic Count Operation........................................................................................ 10.3.2 T2CNT Count Timing.......................................................................................... 10.4 Interrupts............................................................................................................................ 10.4.1 Interrupt Source.................................................................................................... 10.4.2 Timing of Compare Match Flag Setting .............................................................. 10.4.3 Timing of Compare Match Flag Clearing ............................................................
175 176 176 176 177 177 177 178
Section 11 Compare Match Timer (CMT) ................................................................... 179
11.1 Overview............................................................................................................................ 11.1.1 Features ................................................................................................................ 11.1.2 Block Diagram...................................................................................................... 11.1.3 Register Configuration ......................................................................................... 11.2 Register Descriptions......................................................................................................... 11.2.1 Compare Match Timer Start Register (CMSTR) ................................................. 11.2.2 Compare Match Timer Control/Status Register (CMCSR).................................. 11.2.3 Compare Match Timer Counter (CMCNT).......................................................... 11.2.4 Compare Match Timer Constant Register (CMCOR).......................................... 11.3 Operation ........................................................................................................................... 11.3.1 Period Count Operation........................................................................................ 11.3.2 CMCNT Count Timing ........................................................................................ 11.4 Interrupts............................................................................................................................ 11.4.1 Interrupt Sources .................................................................................................. 11.4.2 Compare Match Flag Set Timing ......................................................................... 11.4.3 Compare Match Flag Clear Timing...................................................................... 11.5 Notes on Use...................................................................................................................... 11.5.1 Contention between CMCNT Write and Compare Match ................................... 11.5.2 Contention between CMCNT Word Write and Incrementation .......................... 11.5.3 Contention between CMCNT Byte Write and Incrementation ............................ 179 179 180 181 182 182 183 184 185 185 185 186 186 186 186 187 188 188 189 190
Section 12 Serial Communication Interface (SCI) .................................................... 191
12.1 Overview............................................................................................................................ 12.1.1 Features ................................................................................................................ 12.1.2 Block Diagram...................................................................................................... 12.1.3 Pin Configuration ................................................................................................. 12.1.4 Register Configuration ......................................................................................... 12.2 Register Descriptions......................................................................................................... 12.2.1 Receive Shift Register (RSR)............................................................................... 12.2.2 Receive Data Register (RDR) .............................................................................. 12.2.3 Transmit Shift Register (TSR).............................................................................. 12.2.4 Transmit Data Register (TDR) ............................................................................ 12.2.5 Serial Mode Register (SMR)................................................................................ 191 191 192 192 193 193 193 194 194 194 195
v
12.2.6 Serial Control Register (SCR).............................................................................. 12.2.7 Serial Status Register (SSR)................................................................................. 12.2.8 Bit Rate Register (BRR)....................................................................................... 12.3 Operation ........................................................................................................................... 12.3.1 Overview .............................................................................................................. 12.3.2 Operation in Asynchronous Mode........................................................................ 12.3.3 Multiprocessor Communication ........................................................................... 12.4 Interrupt ............................................................................................................................. 12.5 Notes on Use......................................................................................................................
197 199 203 211 211 212 221 228 229
Section 13 A/D Converter (A/D)..................................................................................... 231
13.1 Overview............................................................................................................................ 13.1.1 Features ................................................................................................................ 13.1.2 Block Diagram...................................................................................................... 13.1.3 Pin Configuration ................................................................................................. 13.1.4 Register Configuration ......................................................................................... 13.2 Register Descriptions......................................................................................................... 13.2.1 A/D Data Registers A-D (ADDRA-ADDRD).................................................... 13.2.2 A/D Control/Status Register (ADCSR)................................................................ 13.2.3 A/D Control Register (ADCR)............................................................................. 13.3 CPU Interface .................................................................................................................... 13.4 Operation ........................................................................................................................... 13.4.1 Single Mode (SCAN = 0) ..................................................................................... 13.4.2 Scan Mode (SCAN = 1) ....................................................................................... 13.4.3 Input Sampling and A/D Conversion Time.......................................................... 13.4.4 MTU Trigger Input Timing.................................................................................. 13.5 A/D Conversion Precision Definitions.............................................................................. 13.6 Notes on Use...................................................................................................................... 13.6.1 Analog Voltage Settings....................................................................................... 13.6.2 Handling of Analog Input Pins............................................................................. 231 231 232 233 234 234 234 235 237 238 240 240 242 244 246 246 248 248 248
Section 14 Pin Function Controller ................................................................................ 251
14.1 Overview............................................................................................................................ 251 14.2 Register Configuration ...................................................................................................... 251 14.3 Register Descriptions......................................................................................................... 252 14.3.1 Port A I/O Register H (PAIORH) ........................................................................ 252 14.3.2 Port E I/O Register (PEIOR)................................................................................ 252 14.3.3 Port E Control Register 2 (PECR2)...................................................................... 253
Section 15 I/O Ports (I/O).................................................................................................. 255
15.1 Overview............................................................................................................................ 255 15.2 Port A................................................................................................................................. 255 15.2.1 Register Configuration ......................................................................................... 255
vi
15.2.2 Port A Data Register H (PADRH)........................................................................ 15.3 Port E ................................................................................................................................. 15.3.1 Register Configuration ......................................................................................... 15.3.2 Port E Data Register (PEDR) ...............................................................................
256 257 257 258
Section 16 RAM ................................................................................................................... 261
16.1 Overview............................................................................................................................ 261
Section 17 Electrical Characteristics.............................................................................. 263
17.1 Absolute Maximum Ratings.............................................................................................. 17.2 DC Characteristics ............................................................................................................. 17.3 AC Characteristics ............................................................................................................. 17.3.1 Clock Timing........................................................................................................ 17.3.2 Control Signal Timing.......................................................................................... 17.3.3 Bus Timing ........................................................................................................... 17.3.4 Multifunction Timer Pulse Unit Timing .............................................................. 17.3.5 I/O Port Timing .................................................................................................... 17.3.6 Serial Communication Interface Timing.............................................................. 17.3.7 A/D Converter Timing ......................................................................................... 17.3.8 Measurement Conditions for AC Characteristic .................................................. 17.4 A/D Converter Characteristics .......................................................................................... 263 264 266 266 268 270 274 275 276 277 278 279
Appendix A On-Chip Supporting Module Registers ................................................ 281 Appendix B Pin States........................................................................................................ 285
B.1 B.2 Pin States ........................................................................................................................... 285 Bus Related Signal Pin States............................................................................................ 286
Appendix C Package Dimensions ................................................................................... 287
vii
Section 1 SH7011 Overview
1.1 SH7011 Overview
The SH7011 CMOS single-chip microprocessors integrate a Hitachi-original architecture, highspeed CPU with peripheral functions required for system configuration. The CPU has a RISC-type instruction set. Most instructions can be executed in one clock cycle, which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low cost, high performance/high-functioning systems, even for applications that were previously impossible with microprocessors, such as real-time control, which demands high speeds. In addition, the SH7011 includes on-chip peripheral functions necessary for system configuration, such as large-capacity ROM, timers, a serial communication interface (SCI), an A/D converter, an interrupt controller, and I/O ports. Memory or peripheral LSIs can be connected efficiently with an external memory access support function. This greatly reduces system cost. 1.1.1 CPU: * Original Hitachi architecture * 32-bit internal data bus * General-register machine Sixteen 32-bit general registers Three 32-bit control registers Four 32-bit system registers * RISC-type instruction set Instruction length: 16-bit fixed length for improved code efficiency Load-store architecture (basic operations are executed between registers) Delayed branch instructions reduce pipeline disruption during branch Instruction set based on C language * Instruction execution time: one instruction/cycle (50 ns/instruction at 20-MHz operation) * Address space: Architecture supports 4 Gbytes * On-chip multiplier: multiplication operations (32 bits x 32 bits 64 bits) and multiplication/accumulation operations (32 bits x 32 bits + 64 bits 64 bits) executed in two to four cycles * Five-stage pipeline
1
SH7011 Features
Interrupt Controller (INTC): * Nine external interrupt pins (NMI, IRQ0 to IRQ7) * Twenty-two internal interrupt sources * Sixteen programmable priority levels Bus State Controller (BSC): * Supports external extended memory access 16-bit external data bus * Memory address space divided into four areas (four areas of SRAM space) with the following settable features: Number of wait cycles (0 to 3 cycles) Outputs chip-select signals for each area * Wait cycles can be inserted using an external WAIT signal Multifunction Timer Pulse Unit (MTU): * Maximum 6 types of waveform output or maximum 6 types of pulse I/O processing possible based on 16-bit timer, 3 channels * 8 dual-use output compare/input capture registers * 8 independent comparators * 6 types of counter input clock * Input capture function * Pulse output mode One shot, toggle, PWM * Multiple counter synchronization function Compare Match Timer (CMT) (Two Channels): * 16-bit free-running counter * One compare register * Generates an interrupt request upon compare match 8-Bit Timers (TIM1, TIM2) (Two Channels): * 8-bit interval timer function * Interrupt generated on counter overflow (TIM1) * Interrupt generated on compare match (TIM2)
2
Serial Communication Interface (SCI) (One Channel): * * * * Asynchronous mode Can transmit and receive simultaneously (full duplex) On-chip dedicated baud rate generator Multiprocessor communication function
I/O Ports: * Input/output: 11 A/D Converter: * 10 bits x 7 channels * Sample & hold function Large Capacity On-Chip Memory: * RAM: 4 kbytes Operating Modes: * Processing states Program execution state Exception processing state * Power-down modes Sleep mode Clock Pulse Generator (CPG): * On-chip clock pulse generator Package: * 100-pin plastic TQFP (TFP-100B)
3
;;;;; ; ;; ;;;;; ;;;;; ;;;; ;; ;; ;; ;;;;; ;; ;; ;;;;; ;;;;; ;;; ;;
PA19 PA18 PE14 PE13 PE12 WAIT CK RD WRH WRL CS3 CS2 CS1 CS0 RXD TXD NMI IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 RES EXTAL XTAL Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss CPU RAM 4 kbytes Interrupt controller Bus state controller Timers 16-bit multifunctional timers x 3, 16-bit compare match timers x 2, 8-bit timers x 2 Serial communication interface (x1 channel) A/D converter Address
1.2
Block Diagram
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D2 D1 D0
4
;
: Peripheral address bus : Peripheral data bus : Internal address bus : Internal upper data bus : Internal lower data bus
Figure 1.1 Block Diagram of the SH7011
TIOC2B/PE7 TIOC2A/PE6 TIOC1B/PE5 TIOC1A/PE4 TIOC0C/PE2 TIOC0A/PE0
AVcc AVss AN6 AN5 AN4 AN3 AN2 AN1 AN0
Data
1.3
1.3.1
Pin Arrangement and Pin Functions
Pin Arrangment
Vss Vcc WAIT Vcc NMI Vss EXTAL Vss XTAL Vss D0 D1 D2 D3 D4 Vss D5 Vcc D6 D7 D8 D9 D10 D11 D12
CK RES PE0/TIOC0A PE2/TIOC0C Vcc PE4/TIOC1A PE5/TIOC1B PE6/TIOC2A Vss AN0 AN1 AN2 AN3 AN4 AN5 AVss AN6 AVcc Vss RXD TXD Vcc PE7TIOC2B PE12 PE13
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
TFP-100B SH7011
D13 D14 D15 IRQ0 Vss IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 CS2 CS3 CS0 CS1 WRL WRH RD Vss A21 Vcc A20 A19 A18
Figure 1.2 SH7011 Pin Arrangement (TFP-100: Top View)
PE14 Vss A1 A2 A3 A4 A5 Vss A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 Vcc A17 Vss PA19 PA18 Vss
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
5
1.3.2
Pin Functions
Table 1.1 lists the pin functions. Table 1.1 Pin Functions
Symbol VCC I/O I Name Supply Function Connects to power supply. Connect all V CC pins to the system supply. No operation will occur if there are any open pins. VSS I Ground Connects to ground. Connect all V SS pins to the system ground. No operation will occur if there are any open pins. Clock EXTAL I External clock Connect a crystal oscillator. Also, an external clock can be input to the EXTAL pin. Connect a crystal oscillator. Supplies the system clock to peripheral devices. Power-on reset when low Non-maskable interrupt request pin. Enables selection of whether to accept on the rising or falling edge. Maskable interrupt request pins. Allows selection of level input and edge input. Outputs addresses. 16-bit bidirectional data bus.
Classification Power supply
XTAL CK System control Interrupts RES NMI
I O I I
Crystal System clock Power-on reset Non-maskable interrupt Interrupt requests 0-7 Address bus Data bus
IRQ0-IRQ7 I
Address bus Data bus Bus control
A1-A21 D0-D15
O I/O
CS0 to CS3 O RD WRH WRL WAIT O O O I
Chip selects 0-3 Chip select signals for external memory or devices. Read Upper write Lower write Wait Indicates reading from an external device. Indicates writing the upper 8 bits (15- 8) of external data. Indicates writing the lower 8 bits (7-0) of external data. Input causes insertion of wait cycles into the bus cycle during external space access.
6
Table 1.1
Pin Functions (cont)
Symbol TIOC0A TIOC0C I/O I/O Name MTU input capture/output compare (channel 0) MTU input capture/output compare (channel 1) MTU input capture/output compare (channel 2) Transmit data Function Channel 0 input capture input/output compare output/PWM output pins.
Classification Multifunction timer/pulse unit (MTU)
TIOC1A TIOC1B
I/O
Channel 1 input capture input/output compare output/PWM output pins.
TIOC2A TIOC2B
I/O
Channel 2 input capture input/output compare output/PWM output pins.
Serial communication interface (SCI)
TxD
O
Transmit data output pins.
RxD A/D Converter AVCC AVSS
I I I
Receive data Analog supply Analog ground Analog input
Receive data input pins. Analog supply; connected to V CC. Analog supply; connected to V SS . Analog signal input pins.
AN0 to AN6 I I/O ports PA18, 19 I/O
Port output enable Input pin for port pin drive control when general use ports are established as output. General purpose General purpose input/output port port pins. Each bit can be designated for input/output.
PE0, 2, 4, to 7, 12 to 14
I/O
7
Section 2 CPU
2.1 Register Configuration
The register set consists of sixteen 32-bit general registers, three 32-bit control registers and four 32-bit system registers. 2.1.1 General Registers (Rn)
The sixteen 32-bit general registers (Rn) are numbered R0-R15. General registers are used for data processing and address calculation. R0 is also used as an index register. Several instructions have R0 fixed as their only usable register. R15 is used as the hardware stack pointer (SP). Saving and recovering the status register (SR) and program counter (PC) in exception processing is accomplished by referencing the stack using R15. Figure 2.1 shows the general registers.
31 R0*1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15, SP (hardware stack pointer)*2 Notes: 1. R0 functions as an index register in the indirect indexed register addressing mode and indirect indexed GBR addressing mode. In some instructions, R0 functions as a fixed source register or destination register. R15 functions as a hardware stack pointer (SP) during exception processing. 0
2.
Figure 2.1 General Registers
9
2.1.2
Control Registers
The 32-bit control registers consist of the 32-bit status register (SR), global base register (GBR), and vector base register (VBR). The status register indicates processing states. The global base register functions as a base address for the indirect GBR addressing mode to transfer data to the registers of on-chip peripheral modules. The vector base register functions as the base address of the exception processing vector area (including interrupts). Figure 2.2 shows a control register.
31 SR 9 8 7 6 5 4 32 1 0 M Q I3 I2 I1 I0 ST SR: Status register T bit: The MOVT, CMP/cond, TAS, TST, BT (BT/S), BF (BF/S), SETT, and CLRT instructions use the T bit to indicate true (1) or false (0). The ADDV, ADDC, SUBV, SUBC, NEGC, DIV0U, DIV0S, DIV1, SHAR, SHAL, SHLR, SHLL, ROTR, ROTL, ROTCR, and ROTCL instructions also use the T bit to indicate carry/borrow or overflow/underflow. S bit: Used by the MAC instruction. Reserved bits. This bit always read 0. The write value should always be 0. Bits I0-I3: Interrupt mask bits. M and Q bits: Used by the DIV0U, DIV0S, and DIV1 instructions. Reserved bits. 0 is read. Write only. 31 GBR 0 Global base register (GBR): Indicates the base address of the indirect GBR addressing mode. The indirect GBR addressing mode is used in data transfer for on-chip peripheral modules register areas and in logic operations. 0 VBR Vector base register (VBR): Stores the base address of the exception processing vector area.
31
Figure 2.2 Control Registers
10
2.1.3
System Registers
System registers consist of four 32-bit registers: high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC). The multiply and accumulate registers store the results of multiply and accumulate operations. The procedure register stores the return address from the subroutine procedure. The program counter stores program addresses to control the flow of the processing. Figure 2.3 shows a system register.
31 MACH MACL 0
Multiply and accumulate (MAC) registers high and low (MACH, MACL): Stores the results of multiply and accumulate operations. Procedure register (PR): Stores a return address from a subroutine procedure. Program counter (PC): Indicates the fourth byte (second instruction) after the current instruction.
31 PR
0
31 PC
0
Figure 2.3 System Registers 2.1.4 Initial Values of Registers
Table 2.1 lists the values of the registers after reset. Table 2.1 Initial Values of Registers
Register R0-R14 R15 (SP) Control registers SR GBR VBR System registers MACH, MACL, PR PC Initial Value Undefined Value of the stack pointer in the vector address table Bits I3-I0 are 1111 (H'F), reserved bits are 0, and other bits are undefined Undefined H'00000000 Undefined Value of the program counter in the vector address table
Classification General registers
11
2.2
2.2.1
Data Formats
Data Format in Registers
Register operands are always longwords (32 bits). When the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register (figure 2.4).
31 Longword 0
Figure 2.4 Longword Operand 2.2.2 Data Format in Memory
Memory data formats are classified into bytes, words, and longwords. Byte data can be accessed from any address, but an address error will occur if you try to access word data starting from an address other than 2n or longword data starting from an address other than 4n. In such cases, the data accessed cannot be guaranteed. The hardware stack area, referred to by the hardware stack pointer (SP, R15), uses only longword data starting from address 4n because this area holds the program counter and status register (figure 2.5).
Address m + 1 Address m 31 Byte Address 2n Address 4n 23 Byte Word Longword 15 Byte Address m + 3 7 Byte Word 0
Address m + 2
Figure 2.5 Byte, Word, and Longword Alignment 2.2.3 Immediate Data Format
Byte (8 bit) immediate data resides in an instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and handled as longword data. Consequently, AND instructions with immediate data always clear the upper 24 bits of the destination register.
12
Word or longword immediate data is not located in the instruction code, but instead is stored in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement.
2.3
2.3.1
Instruction Features
RISC-Type Instruction Set
All instructions are RISC type. This section details their functions. 16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency. One Instruction per Cycle: The microprocessor can execute basic instructions in one cycle using the pipeline system. Instructions are executed in 50 ns at 20 MHz. Data Length: Longword is the standard data length for all operations. Memory can be accessed in bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and handled as longword data. Immediate data is sign-extended for arithmetic operations or zeroextended for logic operations. It also is handled as longword data (table 2.2). Table 2.2 Sign Extension of Word Data
Description Data is sign-extended to 32 bits, and R1 becomes H'00001234. It is next operated upon by an ADD instruction. Example of Conventional CPU ADD.W #H'1234,R0
SH7011 CPU MOV.W ADD @(disp,PC),R1 R1,R0 ......... .DATA.W H'1234
Note: @(disp, PC) accesses the immediate data.
Load-Store Architecture: Basic operations are executed between registers. For operations that involve memory access, data is loaded to the registers and executed (load-store architecture). Instructions such as AND that manipulate bits, however, are executed directly in memory. Delayed Branch Instructions: Unconditional branch instructions are delayed. Executing the instruction that follows the branch instruction and then branching reduces pipeline disruption during branching (table 2.3). There are two types of conditional branch instructions: delayed branch instructions and ordinary branch instructions.
13
Table 2.3
Delayed Branch Instructions
Description Executes an ADD before branching to TRGET Example of Conventional CPU ADD.W BRA R1,R0 TRGET
SH7011 CPU BRA ADD TRGET R1,R0
Multiplication/Accumulation Operation: 16-bit x 16-bit 32-bit multiplication operations are executed in one to two cycles. 16-bit x 16-bit + 64-bit 64-bit multiplication/accumulation operations are executed in two to three cycles. 32-bit x 32-bit 64-bit and 32-bit x 32-bit + 64bit 64-bit multiplication/accumulation operations are executed in two to four cycles. T Bit: The T bit in the status register changes according to the result of the comparison, and in turn is the condition (true/false) that determines if the program will branch. The number of instructions that change the T bit is kept to a minimum to improve the processing speed (table 2.4). Table 2.4 T Bit
Description T bit is set when R0 R1. The program branches to TRGET0 when R0 R1 and to TRGET1 when R0 < R1. Example of Conventional CPU CMP.W BGE BLT R1,R0 TRGET0 TRGET1 #1,R0 TRGET
SH7011 CPU CMP/GE BT BF ADD CMP/EQ BT R1,R0 TRGET0 TRGET1 #1,R0 #0,R0 TRGET
T bit is not changed by ADD. T bit is SUB.W set when R0 = 0. The program BEQ branches if R0 = 0.
Immediate Data: Byte (8 bit) immediate data resides in instruction code. Word or longword immediate data is not input via instruction codes but is stored in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement (table 2.5).
14
Table 2.5
Immediate Data Accessing
SH7011 CPU MOV MOV.W #H'12,R0 @(disp,PC),R0 ................. .DATA.W H'1234 @(disp,PC),R0 ................. .DATA.L H'12345678 MOV.L #H'12345678,R0 Example of Conventional CPU MOV.B MOV.W #H'12,R0 #H'1234,R0
Classification 8-bit immediate 16-bit immediate
32-bit immediate
MOV.L
Note: @(disp, PC) accesses the immediate data.
Absolute Address: When data is accessed by absolute address, the value already in the absolute address is placed in the memory table. Loading the immediate data when the instruction is executed transfers that value to the register and the data is accessed in the indirect register addressing mode (table 2.6). Table 2.6 Absolute Address Accessing
SH7011 CPU MOV.L MOV.B @(disp,PC),R1 @R1,R0 .................. .DATA.L H'12345678 Note: @(disp,PC) accesses the immediate data. Example of Conventional CPU MOV.B @H'12345678,R0
Classification Absolute address
16-Bit/32-Bit Displacement: When data is accessed by 16-bit or 32-bit displacement, the preexisting displacement value is placed in the memory table. Loading the immediate data when the instruction is executed transfers that value to the register and the data is accessed in the indirect indexed register addressing mode (table 2.7). Table 2.7 Displacement Accessing
SH7011 CPU MOV.W MOV.W @(disp,PC),R0 @(R0,R1),R2 .................. .DATA.W H'1234 Note: @(disp,PC) accesses the immediate data. Example of Conventional CPU MOV.W @(H'1234,R1),R2
Classification 16-bit displacement
15
2.3.2
Addressing Modes
Table 2.8 describes addressing modes and effective address calculation. Table 2.8
Addressing Mode Direct register addressing Indirect register addressing Post-increment indirect register addressing
Addressing Modes and Effective Addresses
Instruction Format Effective Addresses Calculation Rn @Rn The effective address is register Rn. (The operand is the contents of register Rn.) The effective address is the content of register Rn. Rn @Rn+ Rn Rn (After the instruction executes) Byte: Rn + 1 Rn Word: Rn + 2 Rn Longword: Rn + 4 Rn Byte: Rn - 1 Rn Word: Rn - 2 Rn Longword: Rn - 4 Rn (Instruction executed with Rn after calculation) Equation -- Rn
The effective address is the content of register Rn. A constant is added to the content of Rn after the instruction is executed. 1 is added for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn Rn + 1/2/4 1/2/4 + Rn
Pre-decrement indirect register addressing
@-Rn
The effective address is the value obtained by subtracting a constant from Rn. 1 is subtracted for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn Rn - 1/2/4 1/2/4 - Rn - 1/2/4
16
Table 2.8
Addressing Mode
Addressing Modes and Effective Addresses (cont)
Instruction Format Effective Addresses Calculation @(disp:4, The effective address is Rn plus a 4-bit Rn) displacement (disp). The value of disp is zeroextended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. Rn disp (zero-extended) x 1/2/4 + Rn + disp x 1/2/4 Equation Byte: Rn + disp Word: Rn + disp x 2 Longword: Rn + disp x 4
Indirect register addressing with displacement
Indirect indexed @(R0, Rn) The effective address is the Rn value plus R0. register Rn addressing + R0 Indirect GBR addressing with displacement @(disp:8, The effective address is the GBR value plus an GBR) 8-bit displacement (disp). The value of disp is zeroextended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. GBR disp (zero-extended) x 1/2/4 + GBR + disp x 1/2/4 Rn + R0
Rn + R0
Byte: GBR + disp Word: GBR + disp x 2 Longword: GBR + disp x 4
17
Table 2.8
Addressing Mode
Addressing Modes and Effective Addresses (cont)
Instruction Format Effective Addresses Calculation Equation GBR + R0
Indirect indexed @(R0, GBR) The effective address is the GBR value plus the R0. GBR addressing GBR + R0 PC relative addressing with displacement @(disp:8, The effective address is the PC value plus an 8-bit PC) displacement (disp). The value of disp is zeroextended, and is doubled for a word operation, and quadrupled for a longword operation. For a longword operation, the lowest two bits of the PC value are masked. PC & H'FFFFFFFC disp (zero-extended) x 2/4 (for longword) PC + disp x 2 or PC & H'FFFFFFFC + disp x 4 GBR + R0
Word: PC + disp x 2 Longword: PC & H'FFFFFFFC + disp x 4
+
18
Table 2.8
Addressing Mode PC relative addressing
Addressing Modes and Effective Addresses (cont)
Instruction Format Effective Addresses Calculation disp:8 The effective address is the PC value sign-extended with an 8-bit displacement (disp), doubled, and added to the PC value. PC disp (sign-extended) x 2 disp:12 The effective address is the PC value sign-extended with a 12-bit displacement (disp), doubled, and added to the PC value. PC disp (sign-extended) x 2 Rn The effective address is the register PC value plus Rn. PC + Rn PC + Rn PC + Rn + PC + disp x 2 PC + disp x 2 + PC + disp x 2 Equation PC + disp x 2
Immediate addressing
#imm:8 #imm:8 #imm:8
The 8-bit immediate data (imm) for the TST, AND, OR, and XOR instructions are zero-extended. The 8-bit immediate data (imm) for the MOV, ADD, and CMP/EQ instructions are sign-extended. The 8-bit immediate data (imm) for the TRAPA instruction is zero-extended and is quadrupled.
-- -- --
19
2.3.3
Instruction Format
Table 2.9 lists the instruction formats for the source operand and the destination operand. The meaning of the operand depends on the instruction code. The symbols are used as follows: * * * * * xxxx: Instruction code mmmm: Source register nnnn: Destination register iiii: Immediate data dddd: Displacement
Table 2.9
Instruction Formats
Source Operand -- 0 xxxx xxxx xxxx -- nnnn: Direct register nnnn: Direct register MOVT Rn Destination Operand -- Example NOP
Instruction Formats 0 format 15 xxxx n format
15 xxxx nnnn xxxx xxxx
0
Control register or system register Control register or system register
STS
MACH,Rn
nnnn: Indirect pre- STC.L decrement register Control register or system register Control register or system register -- -- LDC LDC.L
SR,@-Rn
m format 15 xxxx mmmm xxxx xxxx 0
mmmm: Direct register mmmm: Indirect post-increment register mmmm: Direct register mmmm: PC relative using Rm
Rm,SR @Rm+,SR
JMP BRAF
@Rm Rm
20
Table 2.9
Instruction Formats (cont)
Source Operand Destination Operand mmmm: Direct register 0 nnnn mmmm xxxx mmmm: Direct register mmmm: Indirect post-increment register (multiply/ accumulate) nnnn*: Indirect post-increment register (multiply/ accumulate) mmmm: Indirect post-increment register mmmm: Direct register mmmm: Direct register nnnn: Direct register nnnn: Indirect predecrement register nnnn: Indirect indexed register R0 (Direct register) MOV.L @Rm+,Rn nnnn: Direct register nnnn: Indirect register MACH, MACL Example ADD MOV.L Rm,Rn Rm,@Rn
Instruction Formats nm format 15 xxxx
MAC.W @Rm+,@Rn+
MOV.L
Rm,@-Rn
MOV.L Rm,@(R0,Rn) MOV.B @(disp,Rm),R0
md format 15 xxxx nd4 format 15 xxxx xxxx nnnn dddd nmd format 15 xxxx nnnn mmmm dddd 0 0 xxxx mmmm dddd 0
mmmmdddd: indirect register with displacement R0 (Direct register)
nnnndddd: Indirect register with displacement nnnndddd: Indirect register with displacement nnnn: Direct register
MOV.B R0,@(disp,Rn)
mmmm: Direct register
MOV.L Rm,@(disp,Rn)
mmmmdddd: Indirect register with displacement
MOV.L @(disp,Rm),Rn
Note: In multiply/accumulate instructions, nnnn is the source register.
21
Table 2.9
Instruction Formats (cont)
Source Operand Destination Operand 0 dddddddd: Indirect GBR with displacement R0(Direct register) dddddddd: PC relative with displacement dddddddd: PC relative Example
Instruction Formats d format 15 xxxx xxxx dddd dddd
R0 (Direct register) MOV.L @(disp,GBR),R0
dddddddd: Indirect GBR with displacement
MOV.L R0,@(disp,GBR)
R0 (Direct register) MOVA @(disp,PC),R0 -- -- BF BRA label label
d12 format 15 xxxx dddd dddd dddd nd8 format 15 xxxx i format 15 xxxx xxxx iiii iiii 0 nnnn dddd dddd 0 0
dddddddddddd: PC relative
(label = disp + PC) nnnn: Direct register MOV.L @(disp,PC),Rn
dddddddd: PC relative with displacement iiiiiiii: Immediate iiiiiiii: Immediate
Indirect indexed GBR
AND.B #imm,@(R0,GBR) #imm,R0
R0 (Direct register) AND
iiiiiiii: Immediate ni format 15 xxxx nnnn iiii iiii 0 iiiiiiii: Immediate
-- nnnn: Direct register
TRAPA ADD
#imm #imm,Rn
22
2.4
Instruction Set by Classification
Table 2.10 Classification of Instructions
Operation Classification Types Code Function Data transfer 5 MOV No. of Instructions
Data transfer, immediate data transfer, 39 peripheral module data transfer, structure data transfer Effective address transfer T bit transfer Swap of upper and lower bytes Extraction of the middle of registers connected Binary addition Binary addition with carry Binary addition with overflow check 33
MOVA MOVT SWAP XTRCT Arithmetic operations 21 ADD ADDC ADDV
CMP/cond Comparison DIV1 DIV0S DIV0U DMULS DMULU DT EXTS EXTU MAC MUL MULS MULU NEG NEGC SUB SUBC SUBV Division Initialization of signed division Initialization of unsigned division Signed double-length multiplication Unsigned double-length multiplication Decrement and test Sign extension Zero extension Multiply/accumulate, double-length multiply/accumulate operation Double-length multiply operation Signed multiplication Unsigned multiplication Negation Negation with borrow Binary subtraction Binary subtraction with borrow Binary subtraction with underflow
23
Table 2.10 Classification of Instructions (cont)
Operation Classification Types Code Function Logic operations 6 AND NOT OR TAS TST XOR Shift 10 ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn Branch 9 BF BT BRA BRAF BSR BSRF JMP JSR RTS Logical AND Bit inversion Logical OR Memory test and bit set Logical AND and T bit set Exclusive OR One-bit left rotation One-bit right rotation One-bit left rotation with T bit One-bit right rotation with T bit One-bit arithmetic left shift One-bit arithmetic right shift One-bit logical left shift n-bit logical left shift One-bit logical right shift n-bit logical right shift Conditional branch, conditional branch with delay (Branch when T = 0) Conditional branch, conditional branch with delay (Branch when T = 1) Unconditional branch Unconditional branch Branch to subroutine procedure Branch to subroutine procedure Unconditional branch Branch to subroutine procedure Return from subroutine procedure 11 14 No. of Instructions 14
24
Table 2.10 Classification of Instructions (cont)
Operation Classification Types Code Function System control 11 CLRT CLRMAC LDC LDS NOP RTE SETT SLEEP STC STS TRAPA Total: 62 T bit clear MAC register clear Load to control register Load to system register No operation Return from exception processing T bit set Shift into power-down mode Storing control register data Storing system register data Trap exception handling 142 No. of Instructions 31
Table 2.11 shows the format used in tables 2.12 to 2.17, which list instruction codes, operation, and execution states in order by classification.
25
Table 2.11 Instruction Code Format
Item Instruction Format OP.Sz SRC,DEST Explanation OP: Operation code Sz: Size (B: byte, W: word, or L: longword) SRC: Source DEST: Destination Rm: Source register Rn: Destination register imm: Immediate data disp: Displacement* 1 mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 . . . 1111: R15 iiii: Immediate data dddd: Displacement Direction of transfer Memory operand Flag bits in the SR Logical AND of each bit Logical OR of each bit Exclusive OR of each bit Logical NOT of each bit n-bit left shift n-bit right shift Value when no wait states are inserted*2 Value of T bit after instruction is executed. An em-dash (--) in the column means no change.
Instruction code
MSB LSB
Operation
, (xx) M/Q/T & | ^ ~ <>n
Execution cycles T bit
-- --
Notes: 1. Depending on the operand size, displacement is scaled x1, x2, or x4. For details, see the SH-1/SH-2/SH-DSP Programming Manual. 2. Instruction execution cycles: The execution cycles shown in the table are minimums. The actual number of cycles may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory register) and the register used by the next instruction are the same.
26
Table 2.12 Data Transfer Instructions
Execution Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Instruction MOV #imm,Rn
Instruction Code 1110nnnniiiiiiii 1001nnnndddddddd 1101nnnndddddddd 0110nnnnmmmm0011 0010nnnnmmmm0000 0010nnnnmmmm0001 0010nnnnmmmm0010 0110nnnnmmmm0000 0110nnnnmmmm0001 0110nnnnmmmm0010 0010nnnnmmmm0100 0010nnnnmmmm0101 0010nnnnmmmm0110 0110nnnnmmmm0100 0110nnnnmmmm0101 0110nnnnmmmm0110 10000000nnnndddd 10000001nnnndddd 0001nnnnmmmmdddd 10000100mmmmdddd 10000101mmmmdddd 0101nnnnmmmmdddd 0000nnnnmmmm0100
Operation #imm Sign extension Rn (disp x 2 + PC) Sign extension Rn (disp x 4 + PC) Rn Rm Rn Rm (Rn) Rm (Rn) Rm (Rn) (Rm) Sign extension Rn (Rm) Sign extension Rn (Rm) Rn Rn-1 Rn, Rm (Rn) Rn-2 Rn, Rm (Rn) Rn-4 Rn, Rm (Rn) (Rm) Sign extension Rn,Rm + 1 Rm (Rm) Sign extension Rn,Rm + 2 Rm (Rm) Rn,Rm + 4 Rm R0 (disp + Rn) R0 (disp x 2 + Rn) Rm (disp x 4 + Rn) (disp + Rm) Sign extension R0 (disp x 2 + Rm) Sign extension R0 (disp x 4 + Rm) Rn Rm (R0 + Rn)
MOV.W @(disp,PC),Rn MOV.L @(disp,PC),Rn MOV Rm,Rn
MOV.B Rm,@Rn MOV.W Rm,@Rn MOV.L Rm,@Rn MOV.B @Rm,Rn MOV.W @Rm,Rn MOV.L @Rm,Rn MOV.B Rm,@-Rn MOV.W Rm,@-Rn MOV.L Rm,@-Rn MOV.B @Rm+,Rn MOV.W @Rm+,Rn MOV.L @Rm+,Rn MOV.B R0,@(disp,Rn) MOV.W R0,@(disp,Rn) MOV.L Rm,@(disp,Rn) MOV.B @(disp,Rm),R0 MOV.W @(disp,Rm),R0 MOV.L @(disp,Rm),Rn MOV.B Rm,@(R0,Rn)
27
Table 2.12 Data Transfer Instructions (cont)
Execution Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Instruction MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOVA MOVT Rm,@(R0,Rn) Rm,@(R0,Rn) @(R0,Rm),Rn @(R0,Rm),Rn @(R0,Rm),Rn R0,@(disp,GBR) R0,@(disp,GBR) R0,@(disp,GBR) @(disp,GBR),R0 @(disp,GBR),R0 @(disp,GBR),R0 @(disp,PC),R0 Rn
Instruction Code 0000nnnnmmmm0101 0000nnnnmmmm0110 0000nnnnmmmm1100 0000nnnnmmmm1101 0000nnnnmmmm1110 11000000dddddddd 11000001dddddddd 11000010dddddddd 11000100dddddddd 11000101dddddddd 11000110dddddddd 11000111dddddddd 0000nnnn00101001 0110nnnnmmmm1000 0110nnnnmmmm1001 0010nnnnmmmm1101
Operation Rm (R0 + Rn) Rm (R0 + Rn) (R0 + Rm) Sign extension Rn (R0 + Rm) Sign extension Rn (R0 + Rm) Rn R0 (disp + GBR) R0 (disp x 2 + GBR) R0 (disp x 4 + GBR) (disp + GBR) Sign extension R0 (disp x 2 + GBR) Sign extension R0 (disp x 4 + GBR) R0 disp x 4 + PC R0 T Rn
SWAP.B Rm,Rn SWAP.W Rm,Rn XTRCT Rm,Rn
Rm Swap the bottom two 1 bytes Rn Rm Swap two consecutive words Rn Rm: Middle 32 bits of Rn Rn 1 1
28
Table 2.13 Arithmetic Operation Instructions
Execution Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1
Instruction ADD ADD ADDC ADDV CMP/EQ CMP/EQ CMP/HS CMP/GE CMP/HI CMP/GT CMP/PL CMP/PZ Rm,Rn #imm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rn Rn
Instruction Code 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110 0011nnnnmmmm1111 10001000iiiiiiii 0011nnnnmmmm0000 0011nnnnmmmm0010 0011nnnnmmmm0011 0011nnnnmmmm0110 0011nnnnmmmm0111 0100nnnn00010101 0100nnnn00010001 0010nnnnmmmm1100
Operation Rn + Rm Rn Rn + imm Rn Rn + Rm + T Rn, Carry T Rn + Rm Rn, Overflow T If R0 = imm, 1 T If Rn = Rm, 1 T If RnRm with unsigned data, 1 T If Rn Rm with signed data, 1 T If Rn > Rm with unsigned data, 1 T If Rn > Rm with signed data, 1 T If Rn > 0, 1 T If Rn 0, 1 T If Rn and Rm have an equivalent byte, 1T Single-step division (Rn/Rm) MSB of Rn Q, MSB of Rm M, M ^ Q T 0 M/Q/T
T Bit -- -- Carry Overflow Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Calculation result Calculation result 0
CMP/STR Rm,Rn
DIV1 DIV0S DIV0U
Rm,Rn Rm,Rn
0011nnnnmmmm0100 0010nnnnmmmm0111 0000000000011001
1 1 1
29
Table 2.13 Arithmetic Operation Instructions (cont)
Execution Cycles 2 to 4*
Instruction DMULS.L Rm,Rn
Instruction Code 0011nnnnmmmm1101
Operation Signed operation of Rn x Rm MACH, MACL 32 x 32 64 bit Unsigned operation of Rn x Rm MACH, MACL 32 x 32 64 bit
T Bit --
DMULU.L Rm,Rn
0011nnnnmmmm0101
2 to 4*
--
DT
Rn
0100nnnn00010000
Rn - 1 Rn, when Rn 1 is 0, 1 T. When Rn is nonzero, 0 T A byte in Rm is signextended Rn A word in Rm is signextended Rn A byte in Rm is zeroextended Rn A word in Rm is zeroextended Rn Signed operation of (Rn) x (Rm) + MAC MAC 32 x 32 64 bit Signed operation of (Rn) x (Rm) + MAC MAC 16 x 16 + 64 64 bit Rn x Rm MACL, 32 x 32 32 bit Signed operation of Rn x Rm MAC 16 x 16 32 bit Unsigned operation of Rn x Rm MAC 16 x 16 32 bit 0-Rm Rn 0-Rm-T Rn, Borrow T 1 1 1 1 3/(2 to 4)* 3/(2)*
Comparison result -- -- -- -- --
EXTS.B EXTS.W EXTU.B EXTU.W MAC.L
Rm,Rn Rm,Rn Rm,Rn Rm,Rn @Rm+,@Rn+
0110nnnnmmmm1110 0110nnnnmmmm1111 0110nnnnmmmm1100 0110nnnnmmmm1101 0000nnnnmmmm1111
MAC.W
@Rm+,@Rn+
0100nnnnmmmm1111
--
MUL.L MULS.W
Rm,Rn Rm,Rn
0000nnnnmmmm0111 0010nnnnmmmm1111
2 to 4* 1 to 3*
-- --
MULU.W
Rm,Rn
0010nnnnmmmm1110
1 to 3*
--
NEG NEGC
Rm,Rn Rm,Rn
0110nnnnmmmm1011 0110nnnnmmmm1010
1 1
-- Borrow
30
Table 2.13 Arithmetic Operation Instructions (cont)
Execution Cycles 1 1 1
Instruction SUB SUBC SUBV Rm,Rn Rm,Rn Rm,Rn
Instruction Code 0011nnnnmmmm1000 0011nnnnmmmm1010 0011nnnnmmmm1011
Operation Rn-Rm Rn Rn-Rm-T Rn, Borrow T Rn-Rm Rn, Underflow T
T Bit -- Borrow Overflow
Note: The normal minimum number of execution cycles. (The number in parentheses is the number of cycles when there is contention with following instructions.)
Table 2.14 Logic Operation Instructions
Execution Cycles 1 1 3 1 1 1 3 4 1 1 3 1 1 3
Instruction AND AND Rm,Rn #imm,R0
Instruction Code 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii 0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii 11001111iiiiiiii 0100nnnn00011011 0010nnnnmmmm1000 11001000iiiiiiii 11001100iiiiiiii 0010nnnnmmmm1010 11001010iiiiiiii 11001110iiiiiiii
Operation Rn & Rm Rn R0 & imm R0 (R0 + GBR) & imm (R0 + GBR) ~Rm Rn Rn | Rm Rn R0 | imm R0 (R0 + GBR) | imm (R0 + GBR) If (Rn) is 0, 1 T; 1 MSB of (Rn) Rn & Rm; if the result is 0, 1 T R0 & imm; if the result is 0, 1 T (R0 + GBR) & imm; if the result is 0, 1 T Rn ^ Rm Rn R0 ^ imm R0 (R0 + GBR) ^ imm (R0 + GBR)
T Bit -- -- -- -- -- -- -- Test result Test result Test result Test result -- -- --
AND.B #imm,@(R0,GBR) NOT OR OR OR.B Rm,Rn Rm,Rn #imm,R0 #imm,@(R0,GBR)
TAS.B @Rn TST TST Rm,Rn #imm,R0
TST.B #imm,@(R0,GBR) XOR XOR Rm,Rn #imm,R0
XOR.B #imm,@(R0,GBR)
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Table 2.15 Shift Instructions
Execution Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Instruction ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 SHLL16 SHLR16 Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn
Instruction Code 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 0100nnnn00100000 0100nnnn00100001 0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001
Operation T Rn MSB LSB Rn T T Rn T T Rn T T Rn 0 MSB Rn T T Rn 0 0 Rn T Rn<<2 Rn Rn>>2 Rn Rn<<8 Rn Rn>>8 Rn Rn<<16 Rn Rn>>16 Rn
T Bit MSB LSB MSB LSB MSB LSB MSB LSB -- -- -- -- -- --
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Table 2.16 Branch Instructions
Instruction BF label Instruction Code 10001011dddddddd 10001111dddddddd 10001001dddddddd 10001101dddddddd 1010dddddddddddd 0000mmmm00100011 1011dddddddddddd 0000mmmm00000011 0100mmmm00101011 0100mmmm00001011 0000000000001011 Operation If T = 0, disp x 2 + PC PC; if T = 1, nop Delayed branch, if T = 0, disp x 2 + PC PC; if T = 1, nop If T = 1, disp x 2 + PC PC; if T = 0, nop Delayed branch, if T = 1, disp x 2 + PC PC; if T = 0, nop Delayed branch, disp x 2 + PC PC Delayed branch, Rm + PC PC Delayed branch, PC PR, disp x 2 + PC PC Delayed branch, PC PR, Rm + PC PC Delayed branch, Rm PC Delayed branch, PC PR, Rm PC Delayed branch, PR PC Exec. Cycles 3/1* 3/1* 3/1* 2/1* 2 2 2 2 2 2 2 T Bit -- -- -- -- -- -- -- -- -- -- --
BF/S label BT label
BT/S label BRA label
BRAF Rm BSR label
BSRF Rm JMP JSR RTS @Rm @Rm
Note: One state when it does not branch.
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Table 2.17 System Control Instructions
Instruction CLRT CLRMAC LDC LDC LDC Rm,SR Rm,GBR Rm,VBR Instruction Code 0000000000001000 0000000000101000 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm00000110 0100mmmm00010110 0100mmmm00100110 0000000000001001 0000000000101011 0000000000011000 0000000000011011 SR,Rn GBR,Rn VBR,Rn SR,@-Rn GBR,@-Rn VBR,@-Rn MACH,Rn MACL,Rn PR,Rn 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 0000nnnn00001010 0000nnnn00011010 0000nnnn00101010 Operation 0T 0 MACH, MACL Rm SR Rm GBR Rm VBR (Rm) SR, Rm + 4 Rm (Rm) GBR, Rm + 4 Rm (Rm) VBR, Rm + 4 Rm Rm MACH Rm MACL Rm PR (Rm) MACL, Rm + 4 Rm (Rm) PR, Rm + 4 Rm No operation Delayed branch, stack area PC/SR 1T Sleep SR Rn GBR Rn VBR Rn Rn-4 Rn, SR (Rn) Rn-4 Rn, GBR (Rn) Rn-4 Rn, BR (Rn) MACH Rn MACL Rn PR Rn Exec. Cycles 1 1 1 1 1 3 3 3 1 1 1 T Bit 0 -- LSB -- -- LSB -- -- -- -- -- -- -- -- -- -- 1 -- -- -- -- -- -- -- -- -- --
LDC.L @Rm+,SR LDC.L @Rm+,GBR LDC.L @Rm+,VBR LDS LDS LDS Rm,MACH Rm,MACL Rm,PR
LDS.L @Rm+,MACH LDS.L @Rm+,MACL LDS.L @Rm+,PR NOP RTE SETT SLEEP STC STC STC STC.L STC.L STC.L STS STS STS
(Rm) MACH, Rm + 4 Rm 1 1 1 1 4 1 3* 1 1 1 2 2 2 1 1 1
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Table 2.17 System Control Instructions (cont)
Instruction STS.L STS.L STS.L TRAPA MACH,@-Rn MACL,@-Rn PR,@-Rn #imm Instruction Code 0100nnnn00000010 0100nnnn00010010 0100nnnn00100010 11000011iiiiiiii Operation Rn-4 Rn, MACH (Rn) Rn-4 Rn, MACL (Rn) Rn-4 Rn, PR (Rn) PC/SR stack area, (imm) PC Exec. Cycles 1 1 1 8 T Bit -- -- -- --
Note: The number of execution cycles before the chip enters sleep mode.
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2.5
2.5.1
Processing States
State Transitions
The CPU has four processing states: reset, exception processing, program execution and powerdown. Figure 2.6 shows the transitions between the states.
From only state when RES = 0
Power-on reset state
Reset states
RES = 1 Exception processing state Exception processing source occurs Exception processing ends
Interrupt source occurs
Program execution state
Sleep instruction
Sleep mode
Power-down state
Figure 2.6 Transitions between Processing States Reset State: The CPU resets in the reset state. When the RES pin level goes low, a power-on reset results. Exception Processing State: The exception processing state is a transient state that occurs when exception processing sources such as resets or interrupts alter the CPU's processing state flow.
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For a reset, the initial values of the program counter (PC) (execution start address) and stack pointer (SP) are fetched from the exception processing vector table and stored; the CPU then branches to the execution start address and execution of the program begins. For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status register (SR) are saved to the stack area. The exception service routine start address is fetched from the exception processing vector table; the CPU then branches to that address and the program starts executing, thereby entering the program execution state. Program Execution State: In the program execution state, the CPU sequentially executes the program. Power-Down State: In the power-down state, the CPU operation halts and power consumption declines. The SLEEP instruction places the CPU in the power-down state.
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Section 3 Power-Down State
3.1 Overview
In the power-down state, CPU functions are halted, greatly reducing the power consumption of the chip. 3.1.1 Power-Down State
The power-down state consists of a sleep mode. Table 3.1 shows the conditions for entering sleep mode from the program execution state, the state of the CPU and on-chip peripheral functions in sleep mode, and the methods of exiting sleep mode. Table 3.1 Power-Down State
State Entering Conditions Execution of SLEEP instruction On-Chip Peripheral CPU On-Chip I/O Modules Registers RAM Ports Held Held Held Exiting Methods 1. Interrupt 2. Power-on reset
Mode Sleep
Clock Active
CPU
Halted Active
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3.2
3.2.1
Sleep Mode
Transition to Sleep Mode
When the SLEEP instruction is executed, the chip makes a transition from the program execution state to sleep mode. Immediately after execution of the SLEEP instruction the CPU halts, but the contents of its internal registers are retained. On-chip peripheral modules continue to operate. 3.2.2 Exit from Sleep Mode
Sleep mode is exited by an interrupt or a power-on reset. Exit by Interrupt: When an interrupt is generated, sleep mode is exited and interrupt exception processing is executed. If the priority level of the generated interrupt is not higher than the mask level set in the CPU's status register (SR), or if an interrupt by an on-chip peripheral module is disabled on the module side, the interrupt request will not be accepted and sleep mode will not be exited. Exit by Power-On Reset: When the RES pin is driven low, the chip exits sleep mode and enters the power-on reset state.
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Section 4 Clock Pulse Generator (CPG)
4.1 Overview
The clock pulse generator (CPG) supplies clock pulses within the SH7011 and to external devices. The SH7011's CPG operates the SH7011 at a frequency equal to the oscillation frequency of the crystal resonator. The CPG is composed of an oscillator and a duty adjustment circuit (figure 4.1). There are two ways of generating a clock with the CPG: by connecting a crystal resonator, or by inputting an external clock.
CPG
XTAL Oscillator EXTAL Duty adjustment circuit Internal clock ()
CK (system clock)
Figure 4.1 CPG Block Diagram
4.2
Clock Source
Either a crystal resonator or an external clock can be selected as the clock pulse source. 4.2.1 Crystal Resonator Connection
Circuit Configuration: Figure 4.2 shows the method of connecting a crystal resonator. Use the damping resistance (Rd) shown in table 4.1. An AT-cut parallel-resonance type crystal resonator with the same frequency as the system clock (CK) should be used. Load capacitors (CL1, C L2 ) must be connected as shown in the figure. The clock pulses generated by the crystal resonator and internal oscillator are sent to the duty adjustment circuit. After the duty has been adjusted, the pulses are supplied within the SH7011 chip and to external devices.
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CL1 EXTAL CL2 XTAL Rd
CL1 = CL2 = T.B.D
Figure 4.2 Example of Crystal Resonator Connection Table 4.1 Damping Resistance Value
20 T.B.D.
Frequency (MHz) Rd ()
Crystal Resonator: Figure 4.3 shows an equivalent circuit for the crystal resonator. Use a crystal resonator with the characteristics shown in table 4.2.
L CL Rs
XTAL Co
EXTAL
Figure 4.3 Crystal Resonator Equivalent Circuit Table 4.2 Crystal Resonator Characteristics
Frequency (MHz) Parameter Rs max () Co max (pF) 20 T.B.D. T.B.D.
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4.2.2
External Clock Input
Input the external clock to the EXTAL pin and leave the XTAL pin open (figure 4.4.). The external clock frequency should be the same as that of the system clock (CK).
XTAL
Open
EXTAL
External clock input
Figure 4.4 External Clock Input
4.3
Usage Notes
Note on Board Design: Place the crystal resonator and load capacitors as close as possible to the EXTAL and XTAL pins. To prevent induction from interfering with correct oscillation, ensure that other signal lines to not cross the EXTAL and XTAL pin signal lines.
Avoid crossing signal lines SH7011
CL1
XTAL
CL2
EXTAL
Figure 4.5 Note on Board Design
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Notes on Duty Adjustment: Duty adjustment circuit is performed on an input clock of 5 MHz or higher. With a frequency of less than 5 MHz, duty adjustment may not be performed, but AC characteristics tCH (clock high-level width) and tCL (clock low-level width) are satisfied, and there is no problem with SH7011 internal operation. Figure 4.6 shows the basic characteristics of the duty adjustment circuit. The duty adjustment circuit does not correct for transient fluctuations or jitter in the input clock. Thus, several tens of s are required until duty adjustment is performed and a stable clock is obtained.
70 60 50 40
Input duty 70
Output duty (%)
60 50 40 30
30
1
2
5
10
20
Input frequency (MHz)
Figure 4.6 Duty Adjustment Circuit Characteristics
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Section 5 Exception Processing
5.1
5.1.1
Overview
Types of Exception Processing and Priority
Exception processing is started by four sources: resets, address errors, interrupts and instructions and have the priority shown in table 5.1. When several exception processing sources occur at once, they are processed according to the priority shown. Table 5.1
Exception Reset Address error Interrupt
Types of Exception Processing and Priority Order
Source Power-on reset CPU address error NMI IRQ On-chip peripheral modules: * * * * * * Multifunction timer/pulse unit (MTU) Serial communications interface (SCI) A/D converter (A/D) Compare match timer (CMT) 8-bit timer 1 (TIM1) 8-bit timer 2 (TIM2) Priority High
Instructions Trap instruction (TRAPA instruction) General illegal instructions (undefined code) Illegal slot instructions (undefined code placed directly after a delay branch Low instruction* 1 or instructions that rewrite the PC*2) Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF. 2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF.
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5.1.2
Exception Processing Operations
The exception processing sources are detected and begin processing according to the timing shown in table 5.2. Table 5.2
Exception
Timing of Exception Source Detection and the Start of Exception Processing
Source Timing of Source Detection and Start of Processing Starts when the RES pin changes from low to high. Detected when instruction is decoded and starts when the previous executing instruction finishes executing. Detected when instruction is decoded and starts when the previous executing instruction finishes executing. Trap instruction General illegal instructions Illegal slot instructions Starts from the execution of a TRAPA instruction. Starts from the decoding of undefined code anytime except after a delayed branch instruction (delay slot). Starts from the decoding of undefined code placed in a delayed branch instruction (delay slot) or of instructions that rewrite the PC.
Power-on reset Address error Interrupts Instructions
When exception processing starts, the CPU operates as follows: 1. Exception processing triggered by reset: The initial values of the program counter (PC) and stack pointer (SP) are fetched from the exception processing vector table (PC and SP are respectively the H'00000000 and H'00000004 addresses). See section 5.1.3, Exception Processing Vector Table, for more information. 0 is then written to the vector base register (VBR) and 1111 is written to the interrupt mask bits (I3-I0) of the status register (SR). The program begins running from the PC address fetched from the exception processing vector table. 2. Exception processing triggered by address errors, interrupts and instructions: SR and PC are saved to the stack indicated by R15. For interrupt exception processing, the interrupt priority level is written to the SR's interrupt mask bits (I3-I0). For address error and instruction exception processing, the I3-I0 bits are not affected. The start address is then fetched from the exception processing vector table and the program begins running from that address.
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5.1.3
Exception Processing Vector Table
Before exception processing begins running, the exception processing vector table must be set in memory. The exception processing vector table stores the start addresses of exception service routines. (The reset exception processing table holds the initial values of PC and SP.) All exception sources are given different vector numbers and vector table address offsets, from which the vector table addresses are calculated. During exception processing, the start addresses of the exception service routines are fetched from the exception processing vector table, which indicated by this vector table address. Table 5.3 shows the vector numbers and vector table address offsets. Table 5.4 shows how vector table addresses are calculated. Table 5.3 Exception Processing Vector Table
Vector Numbers PC SP (Reserved by system) 0 1 2 3 General illegal instruction (Reserved by system) Slot illegal instruction (Reserved by system) (Reserved by system) CPU address error (Reserved by system) Interrupts (Reserved by system) NMI 4 5 6 7 8 9 10 11 12 : 31 Trap instruction (user vector) 32 : 63 H'00000010-H'00000013 H'00000014-H'00000017 H'00000018-H'0000001B H'0000001C-H'0000001F H'00000020-H'00000023 H'00000024-H'00000027 H'00000028-H'0000002B H'0000002C-H'0000002F H'00000030-H'00000033 : H'0000007C-H'0000007F H'00000080-H'00000083 : H'000000FC-H'000000FF Vector Table Address Offset H'00000000-H'00000003 H'00000004-H'00000007 H'00000008-H'0000000F
Exception Sources Power-on reset
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Table 5.3
Exception Processing Vector Table (cont)
Vector Numbers IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 On-chip peripheral module* 64 65 66 67 68 69 70 71 72 : 255 Vector Table Address Offset H'00000100-H'00000103 H'00000104-H'00000107 H'00000108-H'0000010B H'0000010C-H'0000010F H'00000110-H'00000113 H'00000114-H'00000117 H'00000118-H'0000011B H'0000011C-H'0000011F H'00000120-H'00000124 : H'000003FC-H'000003FF
Exception Sources Interrupts
Note: The vector numbers and vector table address offsets for each on-chip peripheral module interrupt are given in section 6, Interrupt Controller, table 6.3, Interrupt Exception Processing Vectors and Priorities.
Table 5.4
Calculating Exception Processing Vector Table Addresses
Vector Table Address Calculation Vector table address = (vector table address offset) = (vector number) x 4 Vector table address = VBR + (vector table address offset) = VBR + (vector number) x 4
Exception Source Resets Address errors, interrupts, instructions
Notes: 1. VBR: Vector base register 2. Vector table address offset: See table 5.3. 3. Vector number: See table 5.3.
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5.2
5.2.1
Resets
Reset
A reset has the highest priority of any exception source. As shown in table 5.5, a power-on reset initializes the internal state of the CPU and the on-chip peripheral module registers. Table 5.5 Types of Resets
Conditions for Transition to Reset Status Type Power-on reset RES Low CPU Initialized Internal Status On-Chip Peripheral Module Initialized
5.2.2
Power-On Reset
When the RES pin is driven low, the LSI does a power-on reset. To reliably reset the LSI, the RES pin should be kept at low for at least the duration of the oscillation settling time when applying power or when in standby mode (when the clock circuit is halted) or at least 20 t cyc (when the clock circuit is running). During power-on reset, CPU internal status and all registers of on-chip peripheral modules are initialized. See Appendix B, Pin Status, for the status of individual pins during the power-on reset status. In the power-on reset status, power-on reset exception processing starts when the RES pin is first driven low for a set period of time and then returned to high. The CPU will then operate as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception processing vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3-I0) of the status register (SR) are set to H'F (1111). 4. The values fetched from the exception processing vector table are set in the program counter (PC) and SP and the program begins executing. Be certain to always perform power-on reset processing when turning the system power on.
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5.3
Address Errors
Address errors occur when instructions are fetched or data read or written, as shown in table 5.6. Table 5.6
Bus Cycle Type Instruction fetch Bus Cycle Description Instruction fetched from even address Instruction fetched from odd address Instruction fetched from other than on-chip peripheral module space* Instruction fetched from on-chip peripheral module space* Data read/write Word data accessed from even address Word data accessed from odd address Longword data accessed from other than a longword boundary Byte or word data accessed in on-chip peripheral module space* Longword data accessed in 16-bit on-chip peripheral module space* Longword data accessed in 8-bit on-chip peripheral module space* Note: See section 7, Bus State Controller. Address Errors None (normal) Address error occurs None (normal) Address error occurs None (normal) Address error occurs Address error occurs None (normal) None (normal) Address error occurs
Bus Cycles and Address Errors
5.3.1
Address Error Exception Processing
When an address error occurs, the bus cycle in which the address error occurred ends. When the executing instruction then finishes, address error exception processing starts up. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction. 3. The exception service routine start address is fetched from the exception processing vector table that corresponds to the address error that occurred and the program starts executing from that address. The jump that occurs is not a delayed branch.
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5.4
Interrupts
Table 5.7 shows the sources that start up interrupt exception processing. These are divided into NMI, IRQ and on-chip peripheral modules. Table 5.7
Type NMI IRQ On-chip peripheral module
Interrupt Sources
Request Source NMI pin (external input) IRQ0-IRQ7 (external input) Multifunction timer/pulse unit (MTU) Serial communications interface (SCI) A/D converter Compare match timer (CMT) 8-bit timer 1 8-bit timer 2 Number of Sources 1 8 11 4 1 2 1 1
Each interrupt source is allocated a different vector number and vector table offset. See section 6, Interrupt Controller, table 6.3, Interrupt Exception Processing Vectors and Priorities, for more information on vector numbers and vector table address offsets. 5.4.1 Interrupt Priority Level
The interrupt priority order is predetermined. When multiple interrupts occur simultaneously (overlap), the interrupt controller (INTC) determines their relative priorities and starts up processing according to the results. The priority order of interrupts is expressed as priority levels 0-16, with priority 0 the lowest and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always accepted. The user break interrupt priority level is 15. IRQ interrupts and on-chip peripheral module interrupt priority levels can be set freely using the INTC's interrupt priority level setting registers A through H (IPRA to IPRH) as shown in table 5.8. The priority levels that can be set are 0-15. Level 16 cannot be set. See section 6.3.1, Interrupt Priority Registers A-H (IPRA-IPRH), for more information on IPRA to IPRH.
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Table 5.8
Type NMI IRQ
Interrupt Priority Order
Priority Level 16 0-15 0-15 Comment Fixed priority level. Cannot be masked. Set with interrupt priority level setting registers A through H (IPRA to IPRH). Set with interrupt priority level setting registers A through H (IPRA to IPRH).
On-chip peripheral module
5.4.2
Interrupt Exception Processing
When an interrupt occurs, its priority level is ascertained by the interrupt controller (INTC). NMI is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority level set in the interrupt mask bits (I3-I0) of the status register (SR). When an interrupt is accepted, exception processing begins. In interrupt exception processing, the CPU saves SR and the program counter (PC) to the stack. The priority level value of the accepted interrupt is written to SR bits I3-I0. For NMI, however, the priority level is 16, but the value set in I3-I0 is H'F (level 15). Next, the start address of the exception service routine is fetched from the exception processing vector table for the accepted interrupt, that address is jumped to and execution begins. See section 6.4, Interrupt Operation, for more information on the interrupt exception processing.
5.5
Exceptions Triggered by Instructions
Exception processing can be triggered by trap instructions, general illegal instructions, and illegal slot instructions, as shown in table 5.9. Table 5.9
Type Trap instructions Illegal slot instructions
Types of Exceptions Triggered by Instructions
Source Instruction TRAPA Undefined code placed immediately after a delayed branch instruction (delay slot) and instructions that rewrite the PC Comment -- Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF --
General illegal instructions
Undefined code anywhere besides in a delay slot
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5.5.1
Trap Instructions
When a TRAPA instruction is executed, trap instruction exception processing starts up. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the TRAPA instruction. 3. The exception service routine start address is fetched from the exception processing vector table that corresponds to the vector number specified in the TRAPA instruction. That address is jumped to and the program starts executing. The jump that occurs is not a delayed branch. 5.5.2 Illegal Slot Instructions
An instruction placed immediately after a delayed branch instruction is said to be placed in a delay slot. When the instruction placed in the delay slot is undefined code, illegal slot exception processing starts up when that undefined code is decoded. Illegal slot exception processing also starts up when an instruction that rewrites the program counter (PC) is placed in a delay slot. The processing starts when the instruction is decoded. The CPU handles an illegal slot instruction as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the jump address of the delayed branch instruction immediately before the undefined code or the instruction that rewrites the PC. 3. The exception service routine start address is fetched from the exception processing vector table that corresponds to the exception that occurred. That address is jumped to and the program starts executing. The jump that occurs is not a delayed branch. 5.5.3 General Illegal Instructions
When undefined code placed anywhere other than immediately after a delayed branch instruction (i.e., in a delay slot) is decoded, general illegal instruction exception processing starts up. The CPU handles general illegal instructions the same as illegal slot instructions. Unlike processing of illegal slot instructions, however, the program counter value stored is the start address of the undefined code.
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5.6
When Exception Sources Are Not Accepted
When an address error or interrupt is generated after a delayed branch instruction or interruptdisabled instruction, it is sometimes not accepted immediately but stored instead, as shown in table 5.10. When this happens, it will be accepted when an instruction that can accept the exception is decoded. Table 5.10 Generation of Exception Sources Immediately after a Delayed Branch Instruction or Interrupt-Disabled Instruction
Exception Source Point of Occurrence Immediately after a delayed branch instruction*1 Immediately after an interrupt-disabled instruction*2 Address Error Not accepted Accepted Interrupt Not accepted Not accepted
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF 2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, STS.L
5.6.1
Immediately after a Delayed Branch Instruction
When an instruction placed immediately after a delayed branch instruction (delay slot) is decoded, neither address errors nor interrupts are accepted. The delayed branch instruction and the instruction located immediately after it (delay slot) are always executed consecutively, so no exception processing occurs during this period. 5.6.2 Immediately after an Interrupt-Disabled Instruction
When an instruction immediately following an interrupt-disabled instruction is decoded, interrupts are not accepted. Address errors are accepted.
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5.7
Stack Status after Exception Processing Ends
The status of the stack after exception processing ends is as shown in table 5.11. Table 5.11 Types of Stack Status After Exception Processing Ends
Types Address error Stack Status
SP
Address of instruction 32 bits after executed instruction SR 32 bits
Trap instruction
SP
Address of instruction after TRAPA instruction SR
32 bits 32 bits
General illegal instruction
SP
Start address of illegal instruction SR
32 bits 32 bits
Interrupt
SP
Address of instruction after executed instruction 32 bits SR 32 bits
Illegal slot instruction
SP
Jump destination address of delay branch instruction 32 bits SR 32 bits
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5.8
5.8.1
Notes on Use
Value of Stack Pointer (SP)
The value of the stack pointer must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception processing. 5.8.2 Value of Vector Base Register (VBR)
The value of the vector base register must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception processing. 5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing
When the stack pointer is not a multiple of four, an address error will occur during stacking of the exception processing (interrupts, etc.) and address error exception processing will start up as soon as the first exception processing is ended. Address errors will then also occur in the stacking for this address error exception processing. To ensure that address error exception processing does not go into an endless loop, no address errors are accepted at that point. This allows program control to be shifted to the address error exception service routine and enables error processing. When an address error occurs during exception processing stacking, the stacking bus cycle (write) is executed. During stacking of the status register (SR) and program counter (PC), the SP is -4 for both, so the value of SP will not be a multiple of four after the stacking either. The address value output during stacking is the SP value, so the address where the error occurred is itself output. This means the write data stacked will be undefined.
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Section 6 Interrupt Controller (INTC)
6.1 Overview
The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC has registers for setting the priority of each interrupt which can be used by the user to order the priorities in which the interrupt requests are processed. 6.1.1 Features
The INTC has the following features: * 16 levels of interrupt priority: By setting the eight interrupt-priority level registers, the priorities of IRQ interrupts and on-chip peripheral module interrupts can be set in 16 levels for different request sources. * NMI noise canceler function: NMI input level bits indicate the NMI pin status. By reading these bits with the interrupt exception service routine, the pin status can be confirmed, enabling it to be used as a noise canceler.
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6.1.2
Block Diagram
Figure 6.1 is a block diagram of the INTC.
NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
Input control
Priority ranking judgment
Comparator
Interrupt request
SR I3 I2 I1 I0 MTU CMT SCI A/D TIM1 TIM2 (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) CPU
ICR ISR
IPR
IPRA-IPRH Bus interface Internal bus
Module bus INTC MTU: CMT: SCI: A/D: TIM:
ICR: Interrupt control register Multifunction timer pulse unit ISR: IRQ ststus register Compare match timer Serial communication interface IPRA-IPRH: Interrupt priority level setting registers A to H A/D converter SR: Status register 8-bit timer
Figure 6.1 INTC Block Diagram
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6.1.3
Pin Configuration
Table 6.1 shows the INTC pin configuration. Table 6.1
Name Non-maskable interrupt input pin Interrupt request input pins
Pin Configuration
Abbreviation NMI IRQ0-IRQ7 I/O I I Function Input of non-maskable interrupt request signal Input of maskable interrupt request signals
6.1.4
Register Configuration
The INTC has the 10 registers shown in table 6.2. These registers set the priority of the interrupts and control external interrupt input signal detection. Table 6.2
Name Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H Interrupt control register IRQ status register
Register Configuration
Abbr. IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH ICR ISR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
2
Initial Value Address H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 *
1
Access Sizes 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32
H'FFFF8348 H'FFFF834A H'FFFF834C H'FFFF834E H'FFFF8350 H'FFFF8352 H'FFFF8354 H'FFFF8356 H'FFFF8358 H'FFFF835A
R(W)* H'0000
Notes: 1. The value when the NMI pin is high is H'8000; when the NMI pin is low, it is H'0000. 2. Only 0 can be written, in order to clear flags.
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6.2
Interrupt Sources
There are four types of interrupt sources: NMI, user breaks, IRQ, and on-chip peripheral modules. Each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and 16 the highest). Giving an interrupt a priority level of 0 masks it. 6.2.1 NMI Interrupts
The NMI interrupt has priority 16 and is always accepted. Input at the NMI pin is detected by edge. Use the NMI edge select bit (NMIE) in the interrupt control register (ICR) to select either the rising or falling edge. NMI interrupt exception processing sets the interrupt mask level bits (I3-I0) in the status register (SR) to level 15. 6.2.2 IRQ Interrupts
IRQ interrupts are requested by input from pins IRQ0-IRQ7. Set the IRQ sense select bits (IRQ0S-IRQ7S) of the interrupt control register (ICR) to select low level detection or falling edge detection for each pin. The priority level can be set from 0 to 15 for each pin using the interrupt priority registers A and B (IPRA-IPRB). When IRQ interrupts are set to low level detection, an interrupt request signal is sent to the INTC during the period the IRQ pin is low level. Interrupt request signals are not sent to the INTC when the IRQ pin becomes high level. Interrupt request levels can be confirmed by reading the IRQ flags (IRQ0F-IRQ7F) of the IRQ status register (ISR). When IRQ interrupts are set to falling edge detection, interrupt request signals are sent to the INTC upon detecting a change on the IRQ pin from high to low level. IRQ interrupt request detection results are maintained until the interrupt request is accepted. Confirmation that IRQ interrupt requests have been detected is possible by reading the IRQ flags (IRQ0F-IRQ7F) of the IRQ status register (ISR), and by writing a 0 after reading a 1, IRQ interrupt request detection results can be withdrawn. In IRQ interrupt exception processing, the interrupt mask bits (I3-I0) of the status register (SR) are set to the priority level value of the accepted IRQ interrupt.
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6.2.3
On-Chip Peripheral Module Interrupts
On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral modules: * * * * * * Multifunction timer pulse unit (MTU) Compare match timer (CMT) Serial communications interface (SCI) A/D converter (A/D) 8-bit timer 1 (TIM1) 8-bit timer 2 (TIM2)
A different interrupt vector is assigned to each interrupt source, so the exception service routine does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be assigned to individual on-chip peripheral modules in interrupt priority registers C-H (IPRC- IPRH). On-chip peripheral module interrupt exception processing sets the interrupt mask level bits (I3-I0) in the status register (SR) to the priority level value of the on-chip peripheral module interrupt that was accepted. 6.2.4 Interrupt Exception Vectors and Priority Rankings
Table 6.3 lists interrupt sources and their vector numbers, vector table address offsets and interrupt priorities. Each interrupt source is allocated a different vector number and vector table address offset. Vector table addresses are calculated from vector numbers and address offsets. In interrupt exception processing, the exception service routine start address is fetched from the vector table indicated by the vector table address. See section 5 Exception Processing, table 5.4, Calculating Exception Processing Vector Table Addresses. IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and 15 for each pin or module by setting interrupt priority registers A-H (IPRA-IPRH). The ranking of interrupt sources for IPRC-IPRH, however, must be the order listed under Priority Order Within IPR Setting Range in table 6.3 and cannot be changed. A power-on reset assigns priority level 0 to IRQ interrupts and on-chip peripheral module interrupts. If the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, their priority order is the default priority order indicated at the right in table 6.3.
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Table 6.3
Interrupt Exception Processing Vectors and Priorities
Interrupt Vector Vector No. 11 64 65 66 67 68 69 70 71 TGI0A TGI0B TGI0C TGI0D TCI0V 88 89 90 91 92 Vector Table Address Offset Interrupt Priority (Initial Value) Priority within IPR Setting Default Range Priority -- -- -- -- -- -- -- -- -- High High
Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 MTU0
Corresponding IPR (Bits) -- IPRA (15-12) IPRA (11-8) IPRA (7-4) IPRA (3-0) IPRB (15-12) IPRB (11-8) IPRB (7-4) IPRB (3-0) IPRD (15-12)
H'0000002C to 16 H'0000002F H'00000100 to H'00000103 H'00000104 to H'00000107 H'00000108 to H'0000010B 0 to 15 (0) 0 to 15 (0) 0 to 15 (0)
H'0000010C to 0 to 15 (0) H'0000010F H'00000110 to H'00000113 H'00000114 to H'00000117 H'00000118 to H'0000011B 0 to 15 (0) 0 to 15 (0) 0 to 15 (0)
H'0000011C to 0 to 15 (0) H'0000011F H'00000160 to H'00000163 H'00000164 to H'00000167 H'00000168 to H'0000016B 0 to 15 (0) 0 to 15 (0) 0 to 15 (0)
H'0000016C to 0 to 15 (0) H'0000016F H'00000170 to H'00000173 0 to 15 (0) IPRD (11-8)
Low -- Low
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Table 6.3
Interrupt Exception Processing Vectors and Priorities (cont)
Interrupt Vector Vector No. 96 97 100 104 105 108 132 133 134 135 138 144 148 152 153 Vector Table Address Offset H'00000180 to H'00000183 H'00000184 to H'00000187 H'00000190 to H'00000193 Interrupt Priority (Initial Value) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPRD (3-0) IPRE (15-12) Priority within IPR Setting Default Range Priority High Low -- High Low IPRE (11-8) IPRF (3-0) -- High High
Interrupt Source MTU1 TGI1A TGI1B TCI1V MTU2 TGI2A TGI2B TCI2V SCI ERI RXI TXI TEI A/D CMT0 CMT1 TIM1 TIM2 ADI CMI0 CMI1 ITI CMI
Corresponding IPR (Bits) IPRD (7-4)
H'000001A0 to 0 to 15 (0) H'000001A3 H'000001A4 to 0 to 15 (0) H'000001A7 H'000001B0 to 0 to 15 (0) H'000001B3 H'00000210 to H'00000213 H'00000214 to H'00000217 H'00000218 to H'0000021B H'0000021C to H'0000021F H'00000228 to H'0000022B H'00000240 to H'00000243 H'00000250 to H'00000253 H'00000260 to H'00000263 H'00000264 to H'00000267 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0)
Low IPRG (15-12) IPRG (7-4) IPRG (3-0) IPRH (15-12) -- -- -- High Low Low
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6.3
6.3.1
Description of Registers
Interrupt Priority Registers A-H (IPRA-IPRH)
Interrupt priority registers A-H (IPRA-IPRH) are 16-bit readable/writable registers that set priority levels from 0 to 15 for IRQ interrupts and on-chip peripheral module interrupts. Correspondence between interrupt request sources and each of the IPRA-IPRH bits is shown in table 6.4.
Bit: 15 14 13 12 11 10 9 8
Initial value: R/W: Bit:
0 R/W 7
0 R/W 6
0 R/W 5
0 R/W 4
0 R/W 3
0 R/W 2
0 R/W 1
0 R/W 0
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Table 6.4
Interrupt Request Sources and IPRA-IPRH
Bits
Register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H
15-12 IRQ0 IRQ4 Reserved MTU0 MTU2 Reserved A/D TIM1, 2
11-8 IRQ1 IRQ5 Reserved MTU0 MTTU2 Reserved Reserved Reserved
7-4 IRQ2 IRQ6 Reserved MTU1 Reserved Reserved CMT0 Reserved
3-0 IRQ3 IRQ7 Reserved MTU1 Reserved SCI CMT1 Reserved
As indicated in table 6.4, four IRQ pins or groups of 4 on-chip peripheral modules are allocated to each register. Each of the corresponding interrupt priority ranks are established by setting a value from H'0 (0000) to H'F (1111) in each of the four-bit groups 15-12, 11-8, 7-4 and 3-0. Interrupt priority rank becomes level 0 (lowest) by setting H'0, and level 15 (highest) by setting H'F. 8-bit timers 1 and 2 are set to the same priority rank.
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IPRA-IPRH are initialized to H'0000 by a power-on reset. Reserved bits always return 0 if read, and the write value for these bits should always be 0. 6.3.2 Interrupt Control Register (ICR)
The ICR is a 16-bit register that sets the input signal detection mode of the external interrupt input pin NMI and IRQ0 -IRQ7 and indicates the input signal level to the NMI pin. A power-on reset initializes ICR.
Bit: 15 NMIL Initial value: R/W: Bit: * R 7 IRQ0S Initial value: R/W: 0 R/W 14 -- 0 R 6 IRQ1S 0 R/W 13 -- 0 R 5 IRQ2S 0 R/W 12 -- 0 R 4 IRQ3S 0 R/W 11 -- 0 R 3 IRQ4S 0 R/W 10 -- 0 R 2 IRQ5S 0 R/W 9 -- 0 R 1 IRQ6S 0 R/W 8 NMIE 0 R/W 0 IRQ7S 0 R/W
Note: When NMI input is high: 1; when NMI input is low: 0
* Bit 15--NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can be read to determine the NMI pin level. This bit cannot be modified.
Bit 15: NMIL 0 1 Description NMI input level is low NMI input level is high
* Bits 14 to 9--Reserved: These bits always read as 0. The write value should always be 0. * Bit 8--NMI Edge Select (NMIE)
Bit 8: NMIE 0 1 Description Interrupt request is detected on falling edge of NMI input (initial value) Interrupt request is detected on rising edge of NMI input
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* Bits 7 to 0--IRQ0-IRQ7 Sense Select (IRQ0S-IRQ7S): These bits set the IRQ0-IRQ7 interrupt request detection mode.
Bits 7-0: IRQ0S-IRQ7S 0 1 Description Interrupt request is detected on low level of IRQ input (initial value) Interrupt request is detected on falling edge of IRQ input
6.3.3
IRQ Status Register (ISR)
The ISR is a 16-bit register that indicates the interrupt request status of the external interrupt input pins IRQ0-IRQ7. When IRQ interrupts are set to edge detection, held interrupt requests can be withdrawn by writing a 0 to IRQnF after reading an IRQnF = 1. A power-on reset initializes ISR.
Bit: 15 -- Initial value: R/W: Bit: 0 R 7 IRQ0F Initial value: R/W: 0 R/W 14 -- 0 R 6 IRQ1F 0 R/W 13 -- 0 R 5 IRQ2F 0 R/W 12 -- 0 R 4 IRQ3F 0 R/W 11 -- 0 R 3 IRQ4F 0 R/W 10 -- 0 R 2 IRQ5F 0 R/W 9 -- 0 R 1 IRQ6F 0 R/W 8 -- 0 R 0 IRQ7F 0 R/W
* Bits 15 to 8--Reserved: These bits always read as 0. The write value should always be 0.
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* Bits 7 to 0--IRQ0-IRQ7 Flags (IRQ0F-IRQ7F): These bits display the IRQ0-IRQ7 interrupt request status.
Bits 7-0: IRQ0F-IRQ7F 0 Detection Setting Level detection Description No IRQn interrupt request exists. Clear conditions: When IRQn input is high level Edge detection No IRQn interrupt request was detected. (initial value) Clear conditions: 1. When a 0 is written after reading IRQnF = 1 status 2. When IRQn interrupt exception processing has been executed 1 Level detection An IRQn interrupt request exists. Set conditions: When IRQn input is low level Edge detection An IRQn interrupt request was detected. Set conditions: When a falling edge occurs at an IRQn input
ISR.IRQnF IRQnS (0: level, 1: edge) IRQ pin Level detection Edge detection SQ CPU interrupt request
Selection
RESIRQn
R
(IRQn interrupt acceptance/IRQnF = 0 write after IRQnF = 1 read)
Figure 6.2 External Interrupt Process
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6.4
6.4.1
Interrupt Operation
Interrupt Sequence
The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest priority interrupt in the interrupt requests sent, following the priority levels set in interrupt priority level setting registers A-H (IPRA-IPRH). Lower-priority interrupts are ignored*. If a number of interrupts with the same priority level occur, or if multiple interrupts occur within a single module, the interrupt with the highest default priority or the highest priority within its IPR setting range (as indicated in table 6.3) is selected. 3. The interrupt controller compares the priority level of the selected interrupt request with the interrupt mask bits (I3-I0) in the CPU's status register (SR). If the request priority level is equal to or less than the level set in I3-I0, the request is ignored. If the request priority level is higher than the level in bits I3-I0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. 4. The interrupt controller detects the interrupt request sent from the interrupt controller when it decodes the next instruction to be executed. Instead of executing the decoded instruction, the CPU starts interrupt exception processing (figure 6.4). 5. The status register (SR) and program counter (PC) are saved onto the stack. 6. The priority level of the accepted interrupt is written to bits I3-I0 in SR. 7. The CPU reads the start address of the exception service routine from the exception vector table for the accepted interrupt, jumps to that address, and starts executing the program there. This jump is not a delay branch. Note: An interrupt request for which edge detection has been set is held pending until it is accepted. However, an IRQ interrupt can be cleared by an IRQ status register (ISR) access. For details see section 6.2.3, IRQ Interrupts. Pending edge-detected interrupts are cleared by a power-on reset.
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Program execution state No
Interrupt? Yes NMI? Yes
No
Level 15 interrupt? Yes Yes I3 to I0 level 14? No Yes
No
Level 14 interrupt? Yes I3 to I0 level 13? No Yes
No Level 1 interrupt? Yes I3 to I0 = level 0? No No
Save SR to stack Save PC to stack Copy accept-interrupt level to I3 to I0 Reads exception vector table Branches to exception service routine
I3 to I0: Interrupt mask bits of status register
Figure 6.3 Interrupt Sequence Flowchart
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6.4.2
Stack after Interrupt Exception Processing
Figure 6.4 shows the stack after interrupt exception processing.
Address 4n-8 4n-4 4n PC*1 SR 32 bits 32 bits SP*2
Notes: 1. 2.
PC: Start address of the next instruction (return destination instruction) after the executing instruction Always be certain that SP is a multiple of 4
Figure 6.4 Stack after Interrupt Exception Processing
6.5
Interrupt Response Time
Table 6.5 indicates the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception processing starts and fetching of the first instruction of the interrupt service routine begins. Figure 6.5 shows the pipeline when an IRQ interrupt is accepted.
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Table 6.5
Interrupt Response Time
Number of States
Item Compare identified interrupt priority with SR mask level Wait for completion of sequence currently being executed by CPU
NMI, Peripheral Module 2 or 3
IRQ 4
Notes
X ( 0)
The longest sequence is for interrupt or address-error exception processing (X = 4 + m1 + m2 + m3 + m4). If an interrupt-masking instruction follows, however, the time may be even longer. Performs the PC and SR saves and vector address fetch.
Time from start of interrupt 5 + m1 + m2 + m3 exception processing until fetch of first instruction of exception service routine starts Interrupt response time Total: 7 + m1 + m2 + m3 Minimum: 10 Maximum: 12 + 2 (m1 + m2 + m3) + m4 9 + m1 + m2 + m3 12 13 + 2 (m1 + m2 + m3) + m4
Note: When m1 = m2 = m3 = m4 = 1 m1-m4 are the number of states needed for the following memory accesses. m1: SR save (longword write) m2: PC save (longword write) m3: Vector address read (longword read) m4: Fetch first instruction of interrupt service routine Response time Minimum 7 + m1 + m2 + m3 0.5 s* Maximum 12 + 2 (m1 + m2 + m3) + m4 0.95 s* 9 + m1 + m2 + m3 0.6 s* 13 + 2 (m1 + m2 + m3) + m4 1.0 s*
Note: 20 MHz operation, m1 = m2 = m3 = m4 = 1
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Interrupt acceptance 5 + m1 + m2 + m3 m1 m2 1 m3 1
3 4 IRQ Instruction (instruction replaced by interrupt exception processing) Overrun fetch Interrupt service routine start instruction
FDEEMMEMEE
F FDE
F: Instruction fetch (instruction fetched from memory where program is stored). D: Instruction decoding (fetched instruction is decoded). E: Instruction execution (data operation and address calculation is performed according to the results of decoding). M: Memory access (data in memory is accessed).
Figure 6.5 Pipeline when an IRQ Interrupt is Accepted
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Section 7 Bus State Controller (BSC)
7.1 Overview
The bus state controller (BSC) divides up the address spaces and outputs control for various types of memory. This enables memories like SRAM, and ROM to be linked directly to the LSI without external circuitry. 7.1.1 Features
* Address space is divided into four spaces A maximum linear 4 Mbytes for each of address spaces CS0-CS3 16-bit bus width Wait states can be inserted by software for each space (0-3 waits) In external memory space access, wait states can be inserted by the WAIT pin Outputs control signals for each space according to the type of memory connected * RAM interface On-chip RAM access of 32 bits in 1 state
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7.1.2
Block Diagram
Figure 7.1 shows the BSC block diagram.
Bus interface
WAIT
Wait control unit
WCR1
CS0-CS3
BCR2
RD Memory control unit
WRH, WRL
BSC WCR1: Wait control register 1 BCR2: Bus control register 2
Figure 7.1 BSC Block Diagram
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Module bus
Area control unit
Internal bus
7.1.3
Pin Configuration
Table 7.1 shows the bus state controller pin configuration. Table 7.1
Pin Name A21-A1 D15-D0 CS0-CS3 RD WRH WRL WAIT
Pin Configuration
I/O Output I/O Output Output Output Output Input Function Address output 16-bit data bus Chip select Strobe that indicates a read cycle for ordinary space/multiplex I/O Strobe that indicates an upper byte (D15-D8) write cycle Strobe that indicates a lower byte (D7-D0) write cycle Wait state request signal
7.1.4
Register Configuration
The bus state controller has two registers. The functions of these registers include control of wait states and interfaces with memories such as ROM and SRAM. The registers are summarized in figure table 7.2. Both registers are 16 bits in size, and are initialized by a power-on reset. Table 7.2
Name Bus control register 2 Wait state control register 1
Register Configuration
Abbr. BCR2 WCR1 R/W R/W R/W Initial Value Address H'FFFF H'FFFF Access Size
H'FFFF8622 8, 16 H'FFFF8624 8, 16
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7.1.5
Address Map
Figure 7.2 shows the address format used by the SH7092.
A31-A24
A23, A22
A21
A1
A0
Output address: Output from the address pins CS space selection: Decoded, outputs CS0 to CS3 when A31 to A24 = 00000000 Space selection: Not output externally; used to select the type of space Reserved (do not access) when 00000010 to 11111110 (H'01 to H'FE) On-chip peripheral module space or on-chip RAM space when 11111111 (H'FF)
Figure 7.2 Address Format This LSI uses 32-bit addresses: * A31 to A24 are used to select the type of space and are not output externally. * Bits A23 and A22 are decoded and output as chip select signals (CS0 to CS3) for the corresponding areas when bits A31 to A24 are 00000000. * A21 to A1 are output externally. Table 7.3 shows an address map. Table 7.3
Address H'00200000 to H'003FFFFF H'00400000 to H'007FFFFF H'00800000 to H'00BFFFFF H'00C00000 to H'00FFFFFF H'01000000 to H'FFFF7FFF H'FFFF8000 to H'FFFF87FF
Address Map
Space CS0 space CS1 space CS2 space CS3 space Reserved On-chip peripheral module Reserved Memory Ordinary space Ordinary space Ordinary space Ordinary space Reserved On-chip peripheral module Reserved 6 kbytes 32 bits 2 kbytes 8/16 bits Size 4 Mbytes 4 Mbytes 4 Mbytes 4 Mbytes Bus Width 16 bits 16 bits 16 bits 16 bits
H'FFFF8800 to H'FFFFE7FF H'FFFFE800 to H'FFFFFFFF
On-chip RAM On-chip RAM
Note: Do not access reserved spaces. Operation cannot be guaranteed if they are accessed. 76
7.2
7.2.1
Description of Registers
Bus Control Register 2 (BCR2)
BCR2 is a 16-bit read/write register that specifies the number of idle cycles and CS signal assert extension of each CS space. BCR2 is initialized by power-on resets to H'FFFF.
Bit: 15 IW31 Initial value: R/W: Bit: 1 R/W 7 CW3 Initial value: R/W: 1 R/W 14 IW30 1 R/W 6 CW2 1 R/W 13 IW21 1 R/W 5 CW1 1 R/W 12 IW20 1 R/W 4 CW0 1 R/W 11 IW11 1 R/W 3 SW3 1 R/W 10 IW10 1 R/W 2 SW2 1 R/W 9 IW01 1 R/W 1 SW1 1 R/W 8 IW00 1 R/W 0 SW0 1 R/W
* Bits 15-8--Idles between Cycles (IW31, IW30, IW21, IW20, IW11, IW10, IW01, IW00): These bits specify idle cycles inserted between consecutive accesses when the second one is to a different CS area after a read. Idles are used to prevent data conflict between ROM (and other memories, which are slow to turn the read data buffer off), fast memories, and I/O interfaces. Even when access is to the same area, idle cycles must be inserted when a read access is followed immediately by a write access. The idle cycles to be inserted comply with the area specification of the previous access. Refer to section 7.4, Waits between Access Cycles, for details. IW31, IW30 specify the idle between cycles for CS3 space; IW21, IW20 specify the idle between cycles for CS2 space; IW11, IW10 specify the idle between cycles for CS1 space and IW01, IW00 specify the idle between cycles for CS0 space.
Bit 15 (IW31) 0 Bit 14 (IW30) 0 1 1 0 1 Description No idle cycle after accessing CS3 space Inserts one idle cycle Inserts two idle cycles Inserts three idle cycles (initial value)
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Bit 13 (IW21) 0
Bit 12 (IW20) 0 1
Description No idle cycle after accessing CS2 space Inserts one idle cycle Inserts two idle cycles Inserts three idle cycles (initial value) Description No idle cycle after accessing CS1 space Inserts one idle cycle Inserts two idle cycles Inserts three idle cycles (initial value) Description No idle cycle after accessing CS0 space Inserts one idle cycle Inserts two idle cycles Inserts three idle cycles (initial value)
1
0 1
Bit 11 (IW11) 0
Bit 10 (IW10) 0 1
1
0 1
Bit 9 (IW01) 0
Bit 8 (IW00) 0 1
1
0 1
* Bits 7-4--Idle Specification for Continuous Access (CW3, CW2, CW1, CW0): The continuous access idle specification makes insertions to clearly delineate the bus intervals by once negating the CSn signal when doing consecutive accesses of the same CS space. When a write immediately follows a read, the number of idle cycles inserted is the larger of the two values specified by IW and CW. Refer to section 7.6, Waits between Access Cycles, for details. CW3 specifies the continuous access idles for CS3 space; CW2 specifies the continuous access idles for CS2 space; CW1 specifies the continuous access idles for CS1 space and CW0 specifies the continuous access idles for CS0 space.
Bit 7 (CW3) 0 1 Description No CS3 space continuous access idle cycles One CS3 space continuous access idle cycle (initial value)
Bit 6 (CW2) 0 1
Description No CS2 space continuous access idle cycles One CS2 space continuous access idle cycle (initial value)
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Bit 5 (CW1) 0 1
Description No CS1 space continuous access idle cycles One CS1 space continuous access idle cycle (initial value)
Bit 4 (CW0) 0 1
Description No CS0 space continuous access idle cycles One CS0 space continuous access idle cycle (initial value)
* Bits 3-0--CS Assert Extension Specification (SW3, SW2, SW1, SW0): The CS assert cycle extension specification is for making insertions to prevent extension of the RD signal or WRx signal assert period beyond the length of the CSn signal assert period. Extended cycles insert one cycle before and after each bus cycle, which simplifies interfaces with external devices and also has the effect of extending write data hold time. Refer to section 7.3.3, CS Assert Extension Function, for details. SW3 specifies the CS assert extension for CS3 space access; SW2 specifies the CS assert extension for CS2 space access; SW1 specifies the CS assert extension for CS1 space access and SW0 specifies the CS assert extension for CS0 space access.
Bit 3 (SW3) 0 1 Description No CS3 space CS assert extension CS3 space CS assert extension (initial value) Description No CS2 space CS assert extension CS2 space CS assert extension (initial value) Description No CS1 space CS assert extension CS1 space CS assert extension (initial value) Description No CS0 space CS assert extension CS0 space CS assert extension (initial value)
Bit 2 (SW2) 0 1
Bit 1 (SW1) 0 1
Bit 0 (SW0) 0 1
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7.2.2
Wait Control Register 1 (WCR1)
Wait control register 1 (WCR1) is a 16-bit read/write register that specifies the number of wait cycles (0-3) for each CS space. WCR1 is initialized to H'FFFF by power-on resets.
Bit: 15 -- Initial value: R/W: Bit: 1 R 7 -- Initial value: R/W: 1 R 14 -- 1 R 6 -- 1 R 13 W31 1 R/W 5 W11 1 R/W 12 W30 1 R/W 4 W10 1 R/W 11 -- 1 R 3 -- 1 R 10 -- 1 R 2 -- 1 R 9 W21 1 R/W 1 W01 1 R/W 8 W20 1 R/W 0 W00 1 R/W
* Bits 15 and 14--Reserved. These bits always read 1. The write value should always be 1. * Bits 13 and 12--CS3 Space Wait Specification (W31, W30): These bits specify the number of waits for CS3 space accesses.
Bit 13 (W31) 0 Bit 12 (W30) 0 1 1 0 1 Description No wait (external wait input disabled) 1-wait external wait input enabled 2-wait external wait input enabled 3-wait external wait input enabled (initial value)
* Bits 11 and 10--Reserved. These bits always read 1. The write value should always be 1. * Bits 9 and 8--CS2 Space Wait Specification (W21, W20): These bits specify the number of waits for CS2 space accesses.
Bit 9 (W21) 0 Bit 8 (W20) 0 1 1 0 1 Description No wait (external wait input disabled) 1-wait external wait input enabled 2-wait external wait input enabled 3-wait external wait input enabled (initial value)
80
* Bits 7 and 6--Reserved. These bits always read 1. The write value should always be 1. * Bits 5 and 4--CS1 Space Wait Specification (W11, W10): These bits specify the number of waits for CS1 space accesses.
Bit 5 (W11) 0 Bit 4 (W10) 0 1 1 0 1 Description No wait (external wait input disabled) 1-wait external wait input enabled 2-wait external wait input enabled 3-wait external wait input enabled (initial value)
* Bits 3 and 2--Reserved. These bits always read 1. The write value should always be 1. * Bits 1 and 0--CS0 Space Wait Specification (W01, W00): These bits specify the number of waits for CS0 space accesses.
Bit 1 (W01) 0 Bit 0 (W00) 0 1 1 0 1 Description No wait (external wait input disabled) 1-wait external wait input enabled 2-wait external wait input enabled 3-wait external wait input enabled (initial value)
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7.3
Accessing Ordinary Space
A strobe signal is output by ordinary space accesses to provide primarily for SRAM or ROM direct connections. 7.3.1 Basic Timing
Figure 7.3 shows the basic timing of ordinary space accesses. Ordinary access bus cycles are performed in 2 states.
T1 CK T2
Address
CSn RD Read Data
WRx Write Data
Figure 7.3 Basic Timing of Ordinary Space Access During a read, irrespective of operand size, all bits in the data bus width for the access space (address) are fetched by the LSI on RD, using the required byte locations. During a write, the following signals are associated with transfer of these actual byte locations: WRH (bits 15-8) and WRL (bits 7-0).
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7.3.2
Wait State Control
The number of wait states inserted into ordinary space access states can be controlled using the WCR settings. The specified number of Tw cycles (0-3 waits) are inserted as software wait cycles with the timing shown in figure 7.4.
T1 CK TW T2
Address CSn RD Read Data
WRx Write Data
Figure 7.4 Wait Timing of Ordinary Space Access (Software Wait Only)
83
When the wait is specified by software using WCR, the wait input WAIT signal from outside is sampled. Figure 7.5 shows the WAIT signal sampling. The WAIT signal is sampled at the clock rise one cycle before the clock rise when T w state shifts to T2 state.
T1 CK Address CSn TW TW TW0 T2
RD Read Data WRx Write Data WAIT
Figure 7.5 Wait State Timing of Ordinary Space Access (Wait States from Software Wait 2 State + WAIT Signal)
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7.3.3
CS Assert Period Extension
Idle cycles can be inserted to prevent extension of the RD signal or WRx signal assert period beyond the length of the CSn signal assert period by setting the SW3-SW0 bits of BCR2. This allows for flexible interfaces with external circuitry. The timing is shown in figure 7.6. Th and T f cycles are added respectively before and after the ordinary cycle. Only CSn is asserted in these cycles; RD and WRx signals are not. Further, data is extended up to the Tf cycle, which is effective for gate arrays and the like, which have slower write operations.
Th CK T1 T2 Tf
Address CSn RD Read Data
WRx Write Data
Figure 7.6 CS Assert Period Extension Function
85
7.4
Waits between Access Cycles
When a read from a slow device is completed, data buffers may not go off in time to prevent data conflicts with the next access. If there is a data conflict during memory access, the problem can be solved by inserting a wait in the access cycle. To enable detection of bus cycle starts, waits can be inserted between access cycles during continuous accesses of the same CS space by negating the CSn signal once. 7.4.1 Prevention of Data Bus Conflicts
For the two cases of write cycles after read cycles, and read cycles for a different area after read cycles, waits are inserted so that the number of idle cycles specified by the IW31 to IW00 bits of the BCR2. When idle cycles already exist between access cycles, only the number of empty cycles remaining beyond the specified number of idle cycles are inserted. Figure 7.7 shows an example of idles between cycles. In this example, 1 idle between CSn space cycles has been specified, so when a CSm space write immediately follows a CSn space read cycle, 1 idle cycle is inserted.
T1 CK Address T2 Tidle T1 T2
CSn CSm
RD WRx Data
CSn space read
Idle cycle
CSm space write
Figure 7.7 Idle Cycle Insertion Example
86
IW31 and IW30 specify the number of idle cycles required after a CS3 space read either to read other external spaces, or for this LSI, to do write accesses. In the same manner, IW21 and IW20 specify the number of idle cycles after a CS2 space read, IW11 and IW10, the number after a CS1 space read, and IW01 and IW00, the number after a CS0 space read. 0 to 3 cycles can be specified for CS space. 7.4.2 Simplification of Bus Cycle Start Detection
For consecutive accesses of the same CS space, waits are inserted so that the number of idle cycles designated by the CW3 to CW0 bits of the BCR2 occur. However, for write cycles after reads, the number of idle cycles inserted will be the larger of the two values defined by the IW and CW bits. When idle cycles already exist between access cycles, waits are not inserted. Figure 7.8 shows an example. A continuous access idle is specified for CSn space, and CSn space is consecutively write accessed.
T1 CK Address T2 Tidle T1 T2
CSn
RD WRx Data
CSn space access
Idle cycle
CSn space access
Figure 7.8 Same Space Consecutive Access Idle Cycle Insertion Example
87
7.5
Memory Connection Examples
256k x 16 bits ROM CSn RD A1-A18 D0-D15 CE OE A0-A17 I/O0-I/O15
SH7011
Figure 7.9 16-Bit Data Bus Width ROM Connection
128k x 8 bits SRAM CS OE A0-A16 WE I/O0-I/O7
SH7011 CSn RD A1-A17 WRH D8-D15 WRL D0-D7
CS OE A0-A16 WE I/O0-I/O7
Figure 7.10 16-Bit Data Bus Width SRAM Connection
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Section 8 Multifunction Timer Pulse Unit (MTU)
8.1 Overview
The SH microprocessor has an on-chip 16-bit multifunction timer pulse unit (MTU) with three channels of 16-bit timers. 8.1.1 Features
* Can process a maximum of six different pulse outputs and inputs. * Has eight timer general registers (TGR), four for channel 0 and two each for channels 1 and 2, that can be set to function independently as output compare registers or (except for TGR0B and TGR0D of channel 0) as input capture registers. The channel 0 TGRC and TGRD registers can be used as buffer registers. * Can select six counter input clock sources for all channels * All channels can be set for the following operating modes: Compare match waveform output: 0 output/1 output/toggle output selectable. Input capture function: Selectable rising edge, falling edge, or both rising and falling edge detection. Counter clearing function: Counters can be cleared by a compare-match or input capture. Synchronizing mode: Two or more timer counters (TCNT) can be written to simultaneously. Two or more timer counters can be simultaneously cleared by a comparematch or input capture. Counter synchronization functions enable synchronized register input/output. PWM mode: PWM output can be provided with any duty cycle. When combined with the counter synchronizing function, enables up to four-phase* PWM output. Note: * When channels 0 to 2 are set to PWM mode 1 * Channel 0 can be set for buffer operation Input capture register double buffer configuration possible Output compare register automatic re-write possible * Cascade connection operation Can be operated as a 32-bit counter by using the channel 2 input clock for channel 1 overflow/underflow * High speed access via internal 16-bit bus * Eleven interrupt sources Channel 0 has two dual-function compare-match/input capture interrupts, two comparematch interrupts, and one overflow interrupt, which can be requested independently.
89
Channels 1 and 2 have two compare-match/input capture interrupts, one overflow interrupt, and one underflow interrupt which can be requested independently. * A/D converter conversion start trigger can be generated Channel 0 to 2 compare-match/input capture signals can be used as A/D converter conversion start triggers.
90
Table 8.1 summarizes the MTU functions. Table 8.1
Item Counter clocks General registers
MTU Functions
Channel 0 Channel 1 Channel 2
Internal: /1, /4, /16, /64, /256, /1024 Six to each channel TGR0A TGR0B TGR1A TGR1B No TGR2A TGR2B No
General registers/buffer registers Input/output pins
TGR0C TGR0D TIOC0A TIOC0C
TIOC1A
TIOC2A
Counter clear function Compare match output 0 1 Toggle
TGR compare-match or TGR compare-match or TGR compare-match or input capture input capture input capture Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes Yes No Yes Yes
Input capture function Synchronization Buffer operation PWM mode 1 PWM mode 2
A/D conversion start TGR0A compare match TGR1A compare match TGR2A compare match trigger or input capture or input capture or input capture Interrupt sources Compare match/input capture 0A Compare match 0B Compare match/input capture 0C Compare match 0D Overflow Compare match/input capture 1A Compare match/input capture 1B Overflow -- -- Compare match/input capture 2A Compare match/input capture 2B Overflow -- --
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8.1.2
Block Diagram
Figure 8.1 is the block diagram of the MTU.
[Clock input] Internal clock: /1 /4 /16 /64 /256 /1024
Control logic
TSYR
Internal data bus
BUS I/F
Shared
Channel 2 TCR TMDR
TSR
TSTR
A/D conversion start request signal
TGRA
TGRB
TCNT
Channel 0-2 control logic
Channel 1 TCR TMDR
TSR
[I/O pins] Channel 0: TIOC0A TIOC0C Channel 1: TIOC1A TIOC1B Channel 2: TIOC2A TIOC2B
TGRA
TIOR
TIER
TGRB
TCNT
[Interrupt request signal] Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V
TGRC TGRD
TIOR
TIER
TIORH TIORL
Channel 0 TCR TMDR
TSR
Module data bus
TGRA
TGRB
TCNT
Channel 2: TGI2A TGI2B TCI2V
Figure 8.1 MTU Block Diagram
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TIER
8.1.3
Pin Configuration
Table 8.2 summarizes the MTU pins. Table 8.2 Pin Configuration
Pin Name I/O Function I/O TGR0A input capture input/output compare output/PWM output pin I/O TGR0C input capture input/output compare output/PWM output pin I/O TGR1A input capture input/output compare output/PWM output pin I/O TGR1B input capture input/output compare output/PWM output pin I/O TGR2A input capture input/output compare output/PWM output pin I/O TGR2B input capture input/output compare output/PWM output pin
Channel Name 0
Input TIOC0A capture/output compare-match 0A Input TIOC0C capture/output compare-match 0C
1
Input TIOC1A capture/output compare-match 1A Input TIOC1B capture/output compare-match 1B
2
Input TIOC2A capture/output compare-match 2A Input TIOC2B capture/output compare-match 2B
Note: The TIOC pins output undefined values when they are set to input capture and timer output by the pin function controller (PFC).
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8.1.4
Register Configuration
Table 8.3 summarizes the MTU register configuration. Table 8.3 Register Configuration
Abbreviation R/W TSTR TSYR TCR0 TMDR0 R/W R/W R/W R/W Initial Value H'00 H'00 H'00 H'C0 H'00 H'00 H'40 Address H'FFFF8240 H'FFFF8241 H'FFFF8260 H'FFFF8261 H'FFFF8262 H'FFFF8263 H'FFFF8264 H'FFFF8265 H'FFFF8266 H'FFFF8268 H'FFFF826A H'FFFF826C H'FFFF826E H'FFFF8280 H'FFFF8281 H'FFFF8282 H'FFFF8284 H'FFFF8285 H'FFFF8286 H'FFFF8288 H'FFFF828A 16, 32 8 8, 16, 32 8, 16 16, 32 8, 16, 32 Access Size (Bits) *1 8, 16
Channel Name Shared Timer start register Timer synchro register 0 Timer control register 0 Timer mode register 0
Timer I/O control register 0H TIOR0H R/W Timer I/O control register 0L TIOR0L R/W Timer interrupt enable register 0 Timer status register 0 Timer counter 0 General register 0A General register 0B General register 0C General register 0D 1 Timer control register 1 Timer mode register 1 Timer I/O control register 1 Timer interrupt enable register 1 Timer status register 1 Timer counter 1 General register 1A General register 1B TIER0 TSR0 TCNT0 TGR0A TGR0B TGR0C TGR0D TCR1 TMDR1 TIOR1 TIER1 TSR1 TCNT1 TGR1A TGR1B R/W
R/(W)*2 H'C0 R/W R/W R/W R/W R/W R/W R/W R/W R/W H'0000 H'FFFF H'FFFF H'FFFF H'FFFF H'00 H'C0 H'00 H'40
R/(W)*2 H'C0 R/W R/W R/W H'0000 H'FFFF H'FFFF
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Table 8.3
Register Configuration (cont)
Abbreviation R/W TCR2 TMDR2 TIOR2 TIER2 TSR2 TCNT2 TGR2A TGR2B R/W R/W R/W R/W Initial Value H'00 H'C0 H'00 H'40 Address H'FFFF82A0 H'FFFF82A1 H'FFFF82A2 H'FFFF82A4 H'FFFF82A5 H'FFFF82A6 H'FFFF82A8 H'FFFF82AA 16, 32 8 8, 16, 32 Access Size (Bits) *1 8, 16
Channel Name 2 Timer control register 2 Timer mode register 2 Timer I/O control register 2 Timer interrupt enable register 2 Timer status register 2 Timer counter 2 General register 2A General register 2B
R/(W)*2 H'C0 R/W R/W R/W H'0000 H'FFFF H'FFFF
Notes: Do not access empty addresses. 1. 16-bit registers (TCNT, TGR) cannot be read or written in 8-bit units. 2. Write 0 to clear flags.
8.2
8.2.1
MTU Register Descriptions
Timer Control Register (TCR)
The TCR is an 8-bit read/write register for controlling the TCNT counter for each channel. The MTU has three TCR registers, one for each of the channels 0 to 2. TCR is initialized to H'00 by a power-on reset or the standby mode. Channel 0: TCR0
Bit: 7 CCLR2 Initial value: R/W: 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 3 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W
CKEG1 CKEG0 0 R/W 0 R/W
Channels 1, 2: TCR1, TCR2
Bit: 7 -- Initial value: R/W: 0 R 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 3 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W
CKEG1 CKEG0 0 R/W 0 R/W
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* Bits 7-5--Counter Clear 2, 1, 0 (CCLR2, CCLR1, CCLR0): Select the counter clear source for the TCNT counter. Channels 0:
Bit 7: Bit 6: CCLR2 CCLR1 0 0 Bit 5: CCLR0 0 1 1 0 1 1 0 0 1 1 0 1 Description TCNT clear disabled (initial value) TCNT is cleared by TGRA compare-match or input capture TCNT is cleared by TGRB compare-match Synchronizing clear: TCNT is cleared in synchronization with clear of other channel counters operating in sync.*1 TCNT clear disabled TCNT is cleared by TGRC compare-match or input capture* 2 TCNT is cleared by TGRD compare-match*2 Synchronizing clear: TCNT is cleared in synchronization with clear of other channel counters operating in sync* 1
Notes: 1. Setting the SYNC bit of the TSYR to 1 sets the synchronization. 2. When TGRC or TGRD are functioning as buffer registers, TCNT is not cleared because the buffer registers have priority and compare-match/input captures do not occur.
Channels 1, 2:
Bit 7: Bit 6: Reserved*1 CCLR1 0 0 Bit 5: CCLR0 0 1 1 0 1 Description TCNT clear disabled (initial value) TCNT is cleared by TGRA compare-match or input capture TCNT is cleared by TGRB compare-match or input capture Synchronizing clear: TCNT is cleared in synchronization with clear of other channel counters operating in sync* 2
Notes: 1. The bit 7 of channels 1 and 2 is reserved. It always reads 0, and cannot be modified. 2. Setting the SYNC bit of the TSYR to 1 sets the synchronization.
* Bits 4-3--Clock Edge 1, 0 (CKEG1 and CKEG0): CKEG1 and CKEG0 select the input clock edges. When counting is done on both edges of the internal clock the input clock frequency becomes 1/2 (Example: both edges of /4 = rising edge of /2).
96
Bit 4: Bit 3: CKEG1 CKEG0 Description 0 0 1 1 X Count on rising edges (initial value) Count on falling edges Count on both rising and falling edges
Notes: 1. X: 0 or 1, don't care. 2. Internal clock edge selection is effective when the input clock is /4 or slower. These settings are ignored when /1, or the overflow of another channel is selected for the input clock.
* Bits 2-0--Timer Prescaler 2-0 (TPSC2-TPSC0): TPSC2-TPSC0 select the counter clock source for the TCNT. An independent clock source can be selected for each channel. Table 8.4 shows the possible settings for each channel. Table 8.4 MTU Clock Sources
Internal Clock Channel 0 1 2 /1 O O O /4 O O O /16 O O O /64 O O O /256 X O X /1024 X X O Other Channel Overflow X O X
Note: Symbols: O: Setting possible
X: Setting not possible
Channel 0:
Bit 2: Bit 1: TPSC2 TPSC1 0 0 Bit 0: TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: count with /1 (initial value) Internal clock: count with /4 Internal clock: count with /16 Internal clock: count with /64 Reserved (Do not set) Reserved (Do not set) Reserved (Do not set) Reserved (Do not set)
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Channel 1:
Bit 2: Bit 1: TPSC2 TPSC1 0 0 Bit 0: TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: count with /1 (initial value) Internal clock: count with /4 Internal clock: count with /16 Internal clock: count with /64 Reserved (Do not set) Reserved (Do not set) Internal clock: count with /256 Count with the TCNT2 overflow
Channel 2:
Bit 2: Bit 1: TPSC2 TPSC1 0 0 Bit 0: TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: count with /1 (initial value) Internal clock: count with /4 Internal clock: count with /16 Internal clock: count with /64 Reserved (Do not set) Reserved (Do not set) Reserved (Do not set) Internal clock: count with /1024
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8.2.2
Timer Mode Register (TMDR)
The TMDR is an 8-bit read/write register that sets the operating mode for each channel. The MTU has three TMDR registers, one for each channel. TMDR is initialized to H'C0 by a power-on reset. Channel 0: TMDR0
Bit: 7 -- Initial value: R/W: 1 R 6 -- 1 R 5 BFB 0 R/W 4 BFA 0 R/W 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W
Channels 1, 2: TMDR1, TMDR2
Bit: 7 -- Initial value: R/W: 1 R 6 -- 1 R 5 -- 0 R 4 -- 0 R 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W
* Bits 7, 6--Reserved: These bits are reserved. They always read as 1, and cannot be modified. * Bit 5--Buffer Operation B (BFB): Designates whether to use the TGRB register for normal operation, or buffer operation in combination with the TGRD register. When using TGRD as a buffer register, no TGRD register input capture/output compares are generated. This bit is reserved in channels 1 and 2, which have no TGRD registers. It is always read as 0, and cannot be modified.
Bit 5: BFB 0 1 Description TGRB operates normally (initial value) TGRB and TGRD buffer operation
* Bit 4--Buffer Operation A (BFA): Designates whether to use the TGRA register for normal operation, or buffer operation in combination with the TGRC register. When using TGRC as a buffer register, no TGRC register input capture/output compares are generated. This bit is reserved in channels 1 and 2, which have no TGRC registers. It is always read as 0, and cannot be modified.
Bit 4: BFA 0 1 Description TGRA operates normally (initial value) TGRA and TGRC buffer operation
99
* Bits 3-0--Modes 3-0 (MD3-MD0): These bits set the timer operation mode.
Bit 3: MD3 0 Bit 2: MD2 0 Bit 1: MD1 0 Bit 0: MD0 0 1 1 0 1 0 1 1 * * * * * Description Normal operation (initial value) Reserved (do not set) PWM mode 1 PWM mode 2 Reserved (Do not set) Reserved (Do not set)
*: Don't care
8.2.3
Timer I/O Control Register (TIOR)
The TIOR is a register that controls the TGR. The MTU has four TIOR registers, two for channels 0, and one each for channels 1 and 2. TIOR is initialized to H'00 by a power-on reset. Channel 0: TIOR0H
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W
Channels 1, 2: TIOR1, TIOR2
Bit: 7 IOB3 Initial value: R/W: 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W
Bits 7-4--I/O Control B3-B0 (IOB3-IOB0): These bits set the TGRB register function. (TIOR1 and TIOR2 only. TIOR0H is a reserved bit: it always reads 0 and its write value should always be 0.) Bits 3-0--I/O Control A3-B0 (IOA3-IOA0): These bits set the TGRA register function.
100
Channel 0: TIOR0L
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 IOC3 0 R/W 2 IOC2 0 R/W 1 IOC1 0 R/W 0 IOC0 0 R/W
Note: When the TGRC or TGRD registers are set for buffer operation, these settings become ineffective and the operation is as a buffer register.
* Bits 7-4--Reserved. These bits always read 0. The write value should always be 0. * Bits 3-0--I/O Control C3-C0 (IOC3-IOC0): These bits set the TGRC register function. Channel 0 (TIOR0H Register): * Bits 7-4--Reserved. These bits always read 0. The write value should always be 0. * Bits 3-0--I/O Control A3-A0 (IOA3-IOA0): These bits set the TGR0A register function.
Bit 3: IOA3 0 Bit 2: Bit 1: IOA2 IOA1 0 0 Bit 0: IOA0 Description 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 TGR0A is an input capture register TGR0A is an output compare register Output disabled (initial value) Initial output is 0 Output disabled Initial output is 1 Capture input source is the TIOC0A pin Capture input source is channel 1/ count clock Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match Input capture on rising edge Input capture on falling edge Input capture on both edges Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match
Input capture on TCNT1 count up/count down
101
Channel 0 (TIOR0L Register): * Bits 7-4--Reserved. These bits always read 0. The write value should always be 0. * Bits 3-0--I/O Control C3-C0 (IOC3-IOC0): These bits set the TGR0C register function.
Bit 3: IOC3 0 Bit 2: Bit 1: IOC2 IOC1 0 0 Bit 0: IOC0 Description 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Note: When the BFA bit of TMDR0 is set to 1 and TGR0C is being used as a buffer register, these settings become ineffective and input capture/output compares do not occur. TGR0C is an input capture register TGR0C is an output compare register Output disabled (initial value) Initial output is 0 Output disabled Initial output is 1 Capture input source is the TIOC0C pin Capture input source is channel 1/ count clock Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match Input capture on rising edge Input capture on falling edge Input capture on both edges Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match
Input capture on TCNT1 count up/count down
102
Channel 1 (TIOR1 Register): * Bits 7-4--I/O Control B3-B0 (IOB3-IOB0): These bits set the TGR1B register function.
Bit 7: IOB3 0 Bit 6: Bit 5: IOB2 IOB1 0 0 Bit 4: IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 TGR1B is an input capture register Description TGR1B is an output compare register Output disabled (initial value) Initial output is 0 Output disabled Initial output is 1 Capture input source is the TIOC1B pin Capture input source TGR0C compare/match input capture Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match Input capture on rising edge Input capture on falling edge Input capture on both edges Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match
Input capture on channel TGR0C compare-match/input capture generation
103
* Bits 3-0--I/O Control A3-A0 (IOA3-IOA0): These bits set the TGR1A register function.
Bit 3: IOA3 0 Bit 2: Bit 1: IOA2 IOA1 0 0 Bit 0: IOA0 Description 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 TGR1A is an input capture register TGR1A is an output compare register Output disabled (initial value) Initial output is 0 Output disabled Initial output is 1 Capture input source is the TIOC1A pin Capture input source is TGR0A comparematch/input capture Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match Input capture on rising edge Input capture on falling edge Input capture on both edges Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match
Input capture on channel 0/TGR0A compare-match/input capture generation
104
Channel 2 (TIOR2 Register): * Bits 7-4--I/O Control B3-B0 (IOB3-IOB0): These bits set the TGR2B register function.
Bit 7: IOB3 0 Bit 6: Bit 5: IOB2 IOB1 0 0 Bit 4: IOB0 Description 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 TGR2B is an input capture register TGR2B is an output compare register Output disabled (initial value) Initial output is 0 Output disabled Initial output is 1 Capture input source is the TIOC2B pin Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match Input capture on rising edge Input capture on falling edge Input capture on both edges Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match
Input capture on rising edge Input capture on falling edge Input capture on both edges
105
* Bits 3-0--I/O Control A3-A0 (IOA3-IOA0): These bits set the TGR2A register function.
Bit 3: IOA3 0 Bit 2: Bit 1: IOA2 IOA1 0 0 Bit 0: IOA0 Description 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 TGR2A is an input capture register TGR2A is an output compare register Output disabled (initial value) Initial output is 0 Output disabled Initial output is 1 Capture input source is the TIOC2A pin Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match Input capture on rising edge Input capture on falling edge Input capture on both edges Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match
Input capture on rising edge Input capture on falling edge Input capture on both edges
106
8.2.4
Timer Interrupt Enable Register (TIER)
The TIER is an 8-bit register that controls the enable/disable of interrupt requests for each channel. The MTU has three TIER registers, one each for channel. TIER is initialized to H'40 by a poweron reset. Channel 0: TIER0
Bit: 7 TTGE Initial value: R/W: 0 R/W 6 -- 1 R 5 -- 0 R 4 TCIEV 0 R/W 3 TGIED 0 R/W 2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W
Channels 1, 2: TIER1, TIER2
Bit: 7 TTGE Initial value: R/W: 0 R/W 6 -- 1 R 5 -- 0 R 4 TCIEV 0 R/W 3 -- 0 R 2 -- 0 R 1 TGIEB 0 R/W 0 TGIEA 0 R/W
* Bit 7--A/D Conversion Start Request Enable (TTGE): Enables or disables generation of an A/D conversion start request by a TGRA register input capture/compare-match.
Bit 7: TTGE 0 1 Description Disable A/D conversion start requests generation (initial value) Enable A/D conversion start request generation
* Bit 6--Reserved: This bit is reserved. It always reads as 1, and cannot be modified. * Bit 5--Reserved. This bit always reads 0. The write value should always be 0. * Bit 4--Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests when the overflow flag TCFV of the timer status register (TSR) is set to 1.
Bit 4: TCIEV 0 1 Description Disable TCFV interrupt requests (TCIV) (initial value) Enable TCFV interrupt requests (TCIV)
107
* Bit 3--TGR Interrupt Enable D (TGIED): Enables or disables interrupt TGFD requests when the TGFD bit of the channel 0 of the TSR register is set to 0. This bit is reserved for channels 1 and 2. It always reads as 0. The write value should always be 0.
Bit 3: TGIED 0 1 Description Disable interrupt requests (TGID) due to the TGFD bit (initial value) Enable interrupt requests (TGID) due to the TGFD bit
* Bit 2--TGR Interrupt Enable C (TGIEC): Enables or disables TGFC interrupt requests when the TGFC bit of the Channel 0 of the TSR register is set to 1. This bit is reserved for channels 1 and 2. It always reads as 0. The write value should always be 0.
Bit 2: TGIEC 0 1 Description Disable interrupt requests (TGIC) due to the TGFC bit (initial value) Enable interrupt requests (TGIC) due to the TGFC bit
* Bit 1--TGR Interrupt Enable B (TGIEB): Enables or disables TGFB interrupt requests when the TGFB bit of the TSR register is set to 1.
Bit 1: TGIEB 0 1 Description Disable interrupt requests (TGIB) due to the TGFB bit (initial value) Enable interrupt requests (TGIB) due to the TGFB bit
* Bit 0--TGR Interrupt Enable A (TGIEA): Enables or disables TGFA interrupt requests when the TGFA bit of the TSR register is set to 1.
Bit 0: TGIEA 0 1 Description Disable interrupt requests (TGIA) due to the TGFA bit (initial value) Enable interrupt requests (TGIA) due to the TGFA bit
108
8.2.5
Timer Status Register (TSR)
The timer status register (TSR) is an 8-bit register that indicates the status of each channel. The MTU has three TSR registers, one each for channel. TSR is initialized to H'C0 by a power-on reset. Channel 0: TSR0
Bit: 7 -- Initial value: R/W: 1 R 6 -- 1 R 5 -- 0 R 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)* 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)*
Note: Only 0 writes to clear the flags are possible.
Channels 1, 2: TSR1, TSR2
Bit: 7 -- Initial value: R/W: 1 R 6 -- 1 R 5 -- 0 R 4 TCFV 0 R/(W)* 3 -- 0 R 2 -- 0 R 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)*
Note: Only 0 writes to clear the flags are possible.
* Bits 7 and 6--Reserved. These bits always read 1. The write value should always be 1. * Bit 5--Reserved. This bit always reads 0. The write value should always be 0. * Bit 4--Overflow Flag (TCFV): This status flag indicates the occurrence of a TCNT counter overflow.
Bit 4: TCFV 0 1 Description Clear condition: With TCFV =1, a 0 write to TCFV after reading it (initial value) Set condition: When the TCNT value overflows (H'FFFF H'0000)
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* Bit 3--Output Compare Flag D (TGFD): This status flag indicates the occurrence of a channel 0 TGRD register compare-match. This bit is reserved in channels 1 and 2: it always reads 0 and the write value should always be 0.
Bit 3: TGFD 0 1 Description Clear condition: With TGFD = 1, a 0 write to TGFD following a read (initial value) Set condition: When TCNT = TGRD while TGRD is functioning as an output compare register
* Bit 2--Input Capture/Output Compare Flag C (TGFC): This status flag indicates the occurrence of a Channel 0 TGRC register input capture or compare-match. This bit is reserved for channels 1 and 2. It always reads as 0. The write value should always be 0.
Bit 2: TGFC 0 1 Description Clear condition: With TGFC = 1, a 0 write to TGFC following a read (initial value) Set conditions: * * When TGRC is functioning as an output compare register (TCNT = TGRC) When TGRC is functioning as input capture (the TCNT value is sent to TGRC by the input capture signal)
* Bit 1--Output Compare Flag B (TGFB): This status flag indicates the occurrence of a TGRB register compare-match.
Bit 1: TGFB 0 1 Description Clear condition: With TGFB = 1, a 0 write to TGFB following a read (initial value) Set conditions: When TGRB is functioning as an output compare register (TCNT = TGRB)
110
* Bit 0--Input Capture/Output Compare Flag A (TGFA): This status flag indicates the occurrence of a TGRA register input capture or compare-match.
Bit 0: TGFA 0 1 Description Clear condition: With TGFA = 1, a 0 write to TGFA following a read (initial value) Set conditions: * * When TGRA is functioning as an output compare register (TCNT = TGRA) When TGRA is functioning as input capture (the TCNT value is sent to TGRA by the input capture signal)
8.2.6
Timer Counters (TCNT)
The timer counters (TCNT) are 16-bit counters, with one for each channel, for a total of three. The TCNT are initialized to H'0000 by a power-on reset. Accessing the TCNT counters in 8-bit units is prohibited. Always access in 16-bit units. Channel 0: TCNT0 Channel 1: TCNT1 Channel 2: TCNT2
Bit: 15 14 13 12 11 10 9 8
Initial value: R/W: Bit:
0 R/W 7
0 R/W 6
0 R/W 5
0 R/W 4
0 R/W 3
0 R/W 2
0 R/W 1
0 R/W 0
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
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8.2.7
Timer General Register (TGR)
Each timer general register (TGR) is a 16-bit register that can function as either an output compare register or an input capture register. There are a total of eight TGR, four each for channels 0 and two each for channels 1 and 2. The TGRC and TGRD of channels 0 can be set to operate as buffer registers. The TGR register and buffer register combinations are TGRA with TGRC, and TGRB with TGRD. The TGRs are initialized to H'FFFF by a power-on reset. Accessing of the TGRs in 8-bit units is disabled; they may only be accessed in 16-bit units.
Bit: 15 14 13 12 11 10 9 8
Initial value: R/W: Bit:
1 R/W 7
1 R/W 6
1 R/W 5
1 R/W 4
1 R/W 3
1 R/W 2
1 R/W 1
1 R/W 0
Initial value: R/W:
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
8.2.8
Timer Start Register (TSTR)
The timer start register (TSTR) is an 8-bit read/write register that starts and stops the timer counters (TCNT) of channels 0-2. TSTR is initialized to H'00 upon power-on reset.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 CST2 0 R/W 1 CST1 0 R/W 0 CST0 0 R/W
* Bits 7-3--Reserved. These bits always read 0. The write value should always be 0. * Bits 2-0--Counter Start 2-0 (CST2-CST0): Select starting and stopping of the timer counters (TCNT). The corresponding between bits and channels is as follows: CST2: Channel 2 (TCNT2) CST1: Channel 1 (TCNT1) CST0: Channel 0 (TCNT0)
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Bit n: CSTn 0 1
Description TCNTn count is halted (initial value) TCNTn counts
Note: n = 2 to 0. If 0 is written to a CST bit during operation with the TIOC pin in the output state, the counter stops, but the TIOC pin output compare output level is maintained. If a write is performed on the TIOR register while a CST bit is 0, the pin output level is updated to the set initial output value.
8.2.9
Timer Synchro Register (TSYR)
The timer synchro register (TSYR) is an 8-bit read/write register that selects independent or synchronous TCNT counter operation for channels 0-2. Channels for which 1 is set in the corresponding bit will be synchronized. TSYR is initialized to H'00 upon power-on reset.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 SYNC2 0 R/W 1 0
SYNC1 SYNC0 0 R/W 0 R/W
* Bits 7-3--Reserved. These bits always read 0. The write value should always be 0. * Bits 2-0--Timer Synchronization 2-0 (SYNC2-SYNC0): Selects operation independent of, or synchronized to, other channels. Synchronous operation allows synchronous clears due to multiple TCNT synchronous presets and other channel counter clears. A minimum of two channels must have SYNC bits set to 1 for synchronous operation. For synchronization clearing, it is necessary to set the TCNT counter clear sources (the CCLR2-CCLR0 bits of the TCR register), in addition to the SYNC bit. The counter start to channel and bit-to-channel correspondence are indicated in the tables below. SYNC2: Channel 2 (TCNT2) SYNC1: Channel 1 (TCNT1) SYNC0: Channel 0 (TCNT0)
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Bit n: SYNCn 0
Description Timer counter (TCNTn) independent operation (initial value) (TCNTn preset/clear unrelated to other channels) Timer counter synchronous operation* 1 TCNTn synchronous preset/ synchronous clear* 2 possible
1 Note:
1. Minimum of two channel SYNC bits must be set to 1 for synchronous operation. 2. TCNT counter clear sources (CCLR2-CCLR0 bits of the TCR register) must be set in addition to the SYNC bit in order to have clear synchronization. n = 2 to 0.
8.3
8.3.1
Bus Master Interface
16-Bit Registers
The timer counters (TCNT) and general registers (TGR) are 16-bit registers. A 16-bit data bus to the bus master enables 16-bit read/writes. 8-bit read/write is not possible. Always access in 16-bit units. Figure 8.3 shows an example of 16-bit register access operation.
Internal data bus Upper 8 bits Bus master Lower 8 bits TCNTH TCNTL Bus interface
Module data bus
Figure 8.2 16-Bit Register Access Operation (Bus Master TCNT (16 Bit)) 8.3.2 8-Bit Registers
All registers other than the TCNT and general registers (TGR) are 8-bit registers. These are connected to the CPU by a 16-bit data bus, so 16-bit read/writes and as 8-bit read/writes are both possible (figures 8.3, 8.4, 8.5).
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Internal data bus Upper 8 bits Bus master Lower 8 bits Bus interface
Module data bus
TCR
Figure 8.3 8-Bit Register Access Operation (Bus Master TCR (Upper 8 Bits))
Internal data bus Upper 8 bits Bus master Lower 8 bits TMDR Bus interface
Module data bus
Figure 8.4 8-Bit Register Access Operation (Bus Master TMDR (Lower 8 Bits))
Internal data bus Upper 8 bits Bus master Lower 8 bits TCR TMDR Bus interface
Module data bus
Figure 8.5 8-Bit Register Access Operation (Bus Master TCR, TMDR (16 Bit))
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8.4
8.4.1
Operation
Overview
The operation modes are described below. Ordinary Operation: Each channel has a timer counter (TCNT) and general register (TGR). The TCNT is an upcounter and can also operate as a free-running counter, periodic counter or external event counter. General registers (TGR) can be used as output compare registers or input capture registers. Synchronized Operation: The TCNT of a channel set for synchronized operation does a synchronized preset. When any TCNT of a channel operating in the synchronized mode is rewritten, the TCNTs of other channels are simultaneously rewritten as well. The timer synchronization bits of the TSYR registers of multiple channels set for synchronous operation can be set to clear the TCNTs simultaneously. Buffer Operation: When TGR is an output compare register, the buffer register value of the corresponding channel is transferred to the TGR when a compare-match occurs. When TGR is an input capture register, the TCNT counter value is transferred to the TGR when an input capture occur simultaneously the value previously stored in the TGR is transferred to the buffer register. Cascade Connection Operation: The channel 1 and channel 2 counters (TCNT1 and TCNT2) can be connected together to operate as a 32-bit counter. PWM Mode: In PWM mode, a PWM waveform is output. The output level can be set by the TIOR register. Each TGR can be set for PWM waveform output with a duty cycle between 0% and 100%. 8.4.2 Basic Functions
Always select MTU external pin set function using the pin function controller (PFC). Counter Operation: When a start bit (CST0-CST2) in the timer start register (TSTR) is set to 1, the corresponding timer counter (TCNT) starts counting. There are two counting modes: a freerunning mode and a periodic mode. To select the counting operation (figure 8.6): 1. Set bits TPSC2-TPSC0 in the TCR to select the counter clock. At the same time, set bits CKEG1 and CKEG0 in the TCR to select the desired edge of the input clock. 2. To operate as a periodic counter, set the CCLR2-CCLR0 bits in the TCR to select TGR as a clearing source for the TCNT.
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3. Set the TGR selected in step 2 as an output compare register using the timer I/O control register (TIOR). 4. Write the desired cycle value in the TGR selected in step 2. 5. Set the CST bit in the TSTR to 1 to start counting.
Counting mode selection Select counter clock (1)
Periodic counter Select counter clear source Select output compare register Set period Start counting Periodic counter
Free-running counter
(2)
(3)
(4) (5) Start counting Free-running counter (5)
Figure 8.6 Procedure for Selecting the Counting Operation Free-Running Counter Operation Example: A reset of the MTU timer counters (TCNT) leaves them all in the free-running mode. When a bit in the TSTR is set to 1, the corresponding timer counter operates as a free-running counter and begins to increment. When the count overflows from H'FFFF-H'0000, the TCFV bit in the timer status register (TSR) is set to 1. If the TCIEV bit in the timer's corresponding timer interrupt enable register (TIER) is set to 1, the MTU will make an interrupt request to the interrupt controller. After the TCNT overflows, counting continues from H'0000. Figure 8.7 shows an example of free-running counter operation.
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TCNT value H'FFFF
H'0000 Time CST bit TCFV
Figure 8.7 Free-Running Counter Operation Periodic Counter Operation Example: Periodic counter operation is obtained for a given channel's TCNT by selecting compare-match as a TCNT clear source. Set the TGR register for period setting to output compare register and select counter clear upon compare-match using the CCLR2-CCLR0 bits of the timer control register (TCR). After these settings, the TCNT begins incrementing as a periodic counter when the corresponding bit of TSTR is set to 1. When the count matches the TGR register value, the TGF bit in the TSR is set to 1 and the counter is cleared to H'0000. If the TGIE bit of the corresponding TIER is set to 1 at this point, the MTU will make an interrupt request to the interrupt controller. After the compare-match, TCNT continues counting from H'0000. Figure 8.8 shows an example of periodic counting.
TCNT value TGR Counter cleared by TGR compare match
H'0000 Time CST bit Flag cleared by software activation
TGF
Figure 8.8 Periodic Counter Operation
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Compare-Match Waveform Output Function: The MTU can output 0 level, 1 level, or toggle output from the corresponding output pins upon compare-matches. Procedure for selecting the compare-match waveform output operation (figure 8.9): 1. Set the TIOR to select 0 output or 1 output for the initial value, and 0 output, 1 output, or toggle output for compare-match output. The TIOC pin will output the set initial value until the first compare-match occurs. 2. Set a value in the TGR to select the compare-match timing. 3. Set the CST bit in the TSTR to 1 to start counting.
Output selection Select waveform output mode Select output timing Start counting
(1)
(2)
(3)
Figure 8.9 Procedure for Selecting Compare Match Waveform Output Operation Waveform Output Operation (0 Output/1 Output): Figure 8.10 shows 0 output/1 output. In the example, TCNT is a free-running counter, 1 is output upon compare-match A and 0 is output upon compare-match B. When the pin level matches the set level, the pin level does not change.
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TCNT value H'FFFF TGRA TGRB H'0000 TIOCA Time Does not change Does not change 1 output
TIOCB Does not change Does not change
0 output
Figure 8.10 Example of 0 Output/1 Output Waveform Output Operation (Toggle Output): Figure 8.11 shows the toggle output. In the example, the TCNT operates as a periodic counter cleared by compare-match B, with toggle output at both compare-match A and compare-match B.
TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 TIOCA Time Toggle output Toggle output
TIOCB
Figure 8.11 Example of Toggle Output Input Capture Function: In the input capture mode, the TCNT value is transferred into the TGR register when the input edge is detected at the input capture/output compare pin (TIOC). Detection can take place on the rising edge, falling edge, or both edges. Channels 0 and 1 can use other channel counter input clocks or compare-match signals as input capture sources.
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The procedure for selecting the input capture operation (figure 8.12) is: 1. Set the TIOR to select the input capture function of the TGR, then select the input capture source, and rising edge, falling edge, or both edges as the input edge. 2. Set the CST bit in the TSTR to 1 to start the TCNT counting.
Input selection Select input-capture input Start counting Input capture operation (1) (2)
Figure 8.12 Procedure for Selecting Input Capture Operation Input Capture Operation: Figure 8.13 shows input capture. The falling edge of TIOCB and both edges of TIOCA are selected as input capture input edges. In the example, TCNT is set to clear at the input capture of the TGRB register.
Counter cleared by TIOCB input (falling edge)
TCNT value H'0180 H'0160 H'0010 H'0005 H'0000 TIOCA
Time
TGRA TIOCB
H'0005
H'0160
H'0010
TGRB
H'0180
Figure 8.13 Input Capture Operation
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8.4.3
Synchronous Operation
There are two kinds of synchronous operation, synchronized preset and synchronized clear. The synchronized preset operation allows multiple timer counters (TCNT) to be rewritten simultaneously, while the synchronized clear operation allows multiple TCNT counters to be cleared simultaneously using timer control register (TCR) settings. The synchronizing mode can increase the number of TGR registers for a single time base. All five channels can be set for synchronous operation. Procedure for Selecting the Synchronizing Mode (Figure 8.14): 1. Set 1 in the SYNC bit of the timer synchro register (TSYR) to use the corresponding channel in the synchronizing mode. 2. When a value is written in the TCNT in any of the synchronized channels, the same value is simultaneously written in the TCNT in the other channels. 3. Set the counter to clear with output compare/input capture using bits CCLR2-CCLR0 in the TCR. 4. Set the counter clear source to synchronized clear using the CCLR2-CCLR0 bits of the TCR. 5. Set the CST bits for the corresponding channels in the TSTR to 1 to start counting in the TCNT.
Select synchronizing mode Set synchronizing mode (1)
Synchronized preset (2)
Synchronized clear
Set TCNT
Channel that generated clear source? Yes Select counter clear source Start counting
No
(3)
Set counter synchronous clear Start counting
(4)
(5)
(5)
Synchronized preset
Counter clear
Synchronized clear
Figure 8.14 Procedure for Selecting Synchronizing Operation
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Synchronized Operation: Figure 8.15 shows an example of synchronized operation. Channels 0, 1, and 2 are set to synchronized operation and PWM mode 1. Channel 0 is set for a counter clear upon compare-match with TGR0B. Channels 1 and 2 are set for synchronous counter clears by synchronous presets and TGR0B register compare-matches. Accordingly, a three-phase PWM waveform with the data set in the TGR0B register as its PWM period is output from the TIOC0A, TIOC1A, and TIOC2A pins. See section 8.4.6, PWM Mode, for details on the PWM mode.
TCNT0-TCNT2 values TGR0B TGR1B TGR0A TGR2B TGR1A TGR2A H'0000 TIOC0A TIOC1A TIOC2A Time
Synchronized clear on TGR0B compare match
Figure 8.15 Synchronized Operation Example
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8.4.4
Buffer Operation
Buffer operation is a function of channel 0. TGRC and TGRD can be used as buffer registers. Table 8.5 shows the register combinations for buffer operation. Table 8.5
Channel 0
Register Combinations
General Register TGR0A TGR0B Buffer Register TGR0C TGR0D
The buffer operation differs, depending on whether the TGR has been set as an input capture register or an output compare register. When TGR Is an Output Compare Register: When a compare-match occurs, the corresponding channel buffer register value is transferred to the general register. Figure 8.16 shows an example.
Compare match signal Buffer register General register
Comparator
TCNT
Figure 8.16 Compare Match Buffer Operation When TGR Is an Input Capture Register: When an input capture occurs, the timer counter (TCNT) value is transferred to the general register (TGR), and the value that had been held up to that time in the TGR is transferred to the buffer register (figure 8.17).
Input capture signal
Buffer register
General register
TCNT
Figure 8.17 Input Capture Buffer Operation
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Procedure for Setting Buffer Mode (Figure 8.18): 1. Use the timer I/O control register (TIOR) to set the TGR as either an input capture or output compare register. 2. Use the timer mode register (TMDR) BFA, and BFB bits to set the TGR for buffer mode. 3. Set the CST bit in the TSTR to 1 to start the count operation.
Buffer mode
Select TGR function
(1)
Select buffer mode
(2)
Start counting
(3)
Buffer mode
Figure 8.18 Buffer Operation Setting Procedure Buffer Operation Examples--when TGR Is an Output Compare Register: Figure 8.19 shows an example of channel 0 set to PWM mode 1, and the TGRA and TGRC registers set for buffer operation. The TCNT counter is cleared by a compare-match B, and the output is a 1 upon compare-match A and 0 output upon compare-match B. Because buffer mode is selected, a compare-match A changes the output, and the buffer register TGRC value is simultaneously transferred to the general register TGRA. This operation is repeated with each occurrence of a compare-match A. See section 8.4.6, PWM Mode, for details on the PWM mode.
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TCNT value TGR0B H'0450 H'0200 TGR0A H'0000 H'0200 TGR0C Transfer TGR0A TIOC0A H'0200 H'0450 H'0520 H'0450 Time H'0520
Figure 8.19 Buffer Operation Example (Output Compare Register) Buffer Operation Examples--when TGR Is an Input Capture Register: Figure 8.20 shows an example of TGRA set as an input capture register with the TGRA and TGRB registers set for buffer operation. The TCNT counter is cleared by a TGRA register input capture, and the TIOCA pin input capture input edge is selected as both rising and falling edge. Because buffer mode is selected, an input capture A causes the TCNT counter value to be stored in the TGRA register, and the value that was stored in the TGRA up until that time is simultaneously transferred to the TGRC register.
TCNT value H'0F07 H'09FB H'0532 H'0000 TIOC0A TGRA TGRC H'0532 H'0F07 H'0532 H'09FB H'0F07 Time
Figure 8.20 Buffer Operation Example (Input Capture Register)
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8.4.5
Cascade Connection Mode
Cascade connection mode is a function that connects the 16-bit counters of two channels together to act as a 32-bit counter. This function operates by using the TPSC2-TPSC0 bits of the TCR register to set the channel 1 counter clock to count by TCNT2 counter overflow. Table 8.6 shows the cascade connection combinations. Table 8.6 Cascade Connection Combinations
Upper 16 Bits TCNT1 Lower 16 Bits TCNT2
Combination Channel 1, channel 2
Procedure for Setting Cascade Connection Mode (Figure 8.21): 1. Set the TPSC2-TPSC 0 bits of the channel 1 timer control register (TCR) to B'111 to select "count by TCNT2 overflow." 2. Set the CST bits corresponding to the upper and lower 16 bits in the TSTR to 1 to start the count operation.
Cascade connection operation Select cascade connection Start counting Cascade connection operation
(1)
(2)
Figure 8.21 Procedure for Selecting Cascade Connection Mode Cascade Connection Mode Examples--Input Capture: Figure 8.22 shows an example of operation when the TCNT1 counter is set to count on TCNT2 overflow, the TGR1A and TGR2A registers are set as input capture registers, and the TIOC pin rising edge is selected. Through simultaneous input of the rising edge to the TIOC1A and TIOC2A pins, 32-bit data is transferred, with the upper 16 bits to the TGR1A register and the lower 16 bits to the TGR2A register.
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TCNT1 Clock TCNT1 TCNT2 Clock TCNT2 TIOC1A, TIOC2A TGR1A TGR2A H'03A2 H'0000 H'FFFF H'0000 H'0001 H'03A1 H'03A2
Figure 8.22 Cascade Connection Operation Example (Input Capture) 8.4.6 PWM Mode
PWM mode outputs the various PWM waveforms from output pins. Output levels of 0 output, 1 output, or toggle output can be selected as the output level for the compare-match of each TGR. A period can be set for a register by using the TGR compare-match as a counter clear source. All five channels can be independently set to PWM mode. Synchronous operation is also possible. There are two PWM modes: * PWM mode 1 Generates PWM output using the TGRA and TGRB registers, and TGRC and TGRD registers as pairs. The initial output values are those established in the TGRA and TGRC registers. When the values set in TGR registers being used as a pair are equal, output values will not change even if a compare-match occurs. A maximum of 4-phase PWM output is possible for PWM mode 1. * PWM mode 2 Generates PWM output using one TGR register as a period register and another as a duty cycle register. The output value of each pin upon a counter clear is the initial value established by the TIOR register. When the values set in the period register and duty register are equal, output values will not change even if a compare-match occurs.
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Table 8.7 lists the combinations of PWM output pins and registers. Table 8.7 Combinations of PWM Output Pins and Registers
Output Pin Channel 0 (AB pair) 0 (CD pair) 1 2 Register TGR0A TGR0B TGR0C TGR0D TGR1A TGR1B TGR2A TGR2B PWM Mode 1 TIOC0A TIOC0C TIOC1A TIOC2A PWM Mode 2 TIOC 0A TIOC 0B TIOC 0C TIOC 1A TIOC 1B TIOC 2A TIOC 2B
Note: PWM output of the period setting TGR is not possible in PWM mode 2.
Procedure for Selecting the PWM Mode (Figure 8.23): 1. Set bits TPSC2-TPSC0 in the TCR to select the counter clock source. At the same time, set bits CKEG1 and CKEG0 in the TCR to select the desired edge of the input clock. 2. Set bits CCLR2 to CCLR0 in the TCR to select the TGR to be used as a counter clear source. 3. Set the period in the TGR selected in step 2, and the duty cycle in another TGR. 4. Using the timer I/O control register (TIOR), set the TGR selected in step 3 to act as an output compare register, and select the initial value and output value. 5. Set the MD3-MD 0 bits in TMDR to select the PWM mode. 6. Set the CST bit in the TSTR to 1 to let the TCNT start counting.
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PWM mode
Select counter clock
(1)
Select counter clear source
(2)
Select waveform output level
(3)
Set TGR
(4)
Select PWM mode
(5)
Start counting
(6)
PWM mode
Figure 8.23 Procedure for Selecting the PWM Mode PWM Mode Operation Examples--PWM Mode 1 (Figure 8.24): A TGRA register comparematch is used as a TCNT counter clear source, the TGRA register initial output value and output compare output value are both 0, and the TGRB register output compare output value is a 1. In this example, the value established in the TGRA register becomes the period and the value established in the TGRB register becomes the duty cycle.
TCNT value Counter cleared by TGRA compare match TGRA
TGRB H'0000 TIOCA Time
Figure 8.24 PWM Mode Operation Example (Mode 1)
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PWM Mode Operation Examples--PWM Mode 2 (Figure 8.25): Channels 0 and 1 are set for synchronous operation, TGR1B register compare-match is used as a TCNT counter clear source, the other TGR register initial output value is 0 and output compare output value is 1, and a 3-phase PWM waveform is output. In this example, the value established in the TGR1B register becomes the period and the value established in the other TGR register becomes the duty cycle.
TCNTvalue TGR1B TGR1A TGR0C TGR0A H'0000 TIOC0A Time
Counter cleared on TGR1B compare match
TIOC0C
TIOC1A
Figure 8.25 PWM Mode Operation Example (Mode 2) 0% Duty Cycle: Figure 8.26 shows an example of a 0% duty cycle PWM waveform output in PWM mode.
TCNT value TGRB rewrite TGRA TICCA
TGRB
TGRB rewrite
TGRB rewrite Time
0% duty cycle
Figure 8.26 PWM Mode Operation Example (0% Duty Cycle)
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100% Duty Cycle: Figure 8.27 shows an example of a 100% duty cycle PWM waveform output in PWM mode. In PWM mode, when setting cycle = duty cycle the output waveform does not change, nor is there a change of waveform for the first pulse immediately after clearing the counter.
TCNT value TGRA TGRB rewrite
Output does not change if period register and duty cycle register compare matches occur simultaneously
TGRB rewrite TGRB TGRB rewrite Time 100% duty cycle
TCNT value TGRB rewrite TGRA
Output does not change if period register and duty cycle register compare matches occur simultaneously
TGRB rewrite
TGRB TGRB rewrite
Time
100% duty cycle 0% duty cycle
Figure 8.27 PWM Mode Operation Example (100% Duty Cycle)
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8.5
8.5.1
Interrupts
Interrupt Sources and Priority Ranking
The MTU has two interrupt sources: TGR register compare-match/input captures, TCNT counter overflows. Because each of these three types of interrupts are allocated its own dedicated status flag and enable/disable bit, the issuing of interrupt request signals to the interrupt controller can be independently enabled or disabled. When an interrupt source is generated, the corresponding status flag in the timer status register (TSR) is set to 1. If the corresponding enable/disable bit in the timer input enable register (TIER) is set to 1 at this time, the MTU makes an interrupt request of the interrupt controller. The interrupt request is canceled by clearing the status flag to 0. The channel priority order can be changed with the interrupt controller. The priority ranking within a channel is fixed. For more information, see section 6, Interrupt Controller. Table 8.8 lists the MTU interrupt sources. Input Capture/Compare Match Interrupts: If the TGIE bit of the timer input enable register (TIER) is already set to 1 when the TGF flag in the timer status register (TSR) is set to 1 by a TGR register input capture/compare-match of any channel, an interrupt request is sent to the interrupt controller. The interrupt request is canceled by clearing the TGF flag to 0. The MTU has 8 input capture/compare-match interrupts; four each for channel 0, and two each for channels 1 and 2. Overflow Interrupts: If the TCIEV bit of the TIER is already set to 1 when the TCFV flag in the TSR is set to 1 by a TCNT counter overflow of any channel, an interrupt request is sent to the interrupt controller. The interrupt request is canceled by clearing the TCFV flag to 0. The MTU has three overflow interrupts, one for each channel.
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Table 8.8
Channel 0
MTU Interrupt Sources
Interrupt Source TGI0A TGI0B TGI0C TGI0D TCI0V Description TGR0A input capture/compare-match TGR0B input capture/compare-match TGR0C input capture/compare-match TGR0D input capture/compare-match TCNT0 overflow TGR1A input capture/compare-match TGR1B input capture/compare-match TCNT1 overflow TGR2A input capture/compare-match TGR2B input capture/compare-match TCNT2 overflow TCNT2 underflow Low Priority* High
1
TGI1A TGI1B TCI1V
2
TGI2A TGI2B TCI2V TCI2U
Note: Indicates the initial status following reset. The ranking of channels can be altered using the interrupt controller.
8.5.2
A/D Converter Activation
The TGRA register input capture/compare-match of any channel can be used to activate the onchip A/D converter. If the TTGE bit of the TIER is already set to 1 when the TGFA flag in the TSR is set to 1 by a TGRA register input capture/compare-match of any of the channels, an A/D conversion start request is sent to the A/D converter. If the MTU conversion start trigger is selected at such a time on the A/D converter side when this happens, the A/D conversion starts. The MTU has 3 TGRA register input capture/compare-match interrupts, one for each channel, that can be used as A/D converter activation sources.
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8.6
8.6.1
Operation Timing
Input/Output Timing
TCNT Count Timing: Count timing for the TCNT counter with internal clock operation is shown in figure 8.28.
Internal clock TCNT input clock TCNT N-1 N N+1 N+2
Falling edge
Rising edge
Falling edge
Figure 8.28 TCNT Count Timing during Internal Clock Operation Output Compare Output Timing: The compare-match signal is generated at the final state of TCNT and TGR matching. When a compare-match signal is issued, the output value set in TIOR or TOCR is output to the output compare output pin (TIOC pin). After TCNT and TGR matching, a compare-match signal is not issued until immediately before the TCNT input clock. Output compare output timing (normal mode and PWM mode) is shown in figure 8.29.
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TCNT input clock
TCNT
N
N+1
TGR Comparematch signal TIOC pin
N
Figure 8.29 Output Compare Output Timing (Normal Mode/PWM Mode) Input Capture Signal Timing: Figure 8.30 illustrates input capture timing.
Input capture input Input capture signal TCNT N N+1 N+2
Rising edge
Falling edge
TGR
N
N+2
Figure 8.30 Input Capture Input Signal Timing
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Counter Clearing Timing Due to Compare-Match/Input Capture: Timing for counter clearing due to compare-match is shown in figure 8.31. Figure 8.32 shows the timing for counter clearing due to input capture.
Comparematch signal Counter clear signal
TCNT
N
H'0000
TGR
N
Figure 8.31 Counter Clearing Timing (Compare-Match)
Input capture signal Counter clear signal
TCNT
N
H'0000
TGR
N
Figure 8.32 Counter Clearing Timing (Input Capture)
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Buffer Operation Timing: Compare-match buffer operation timing is shown in figure 8.33. Figure 8.34 shows input capture buffer operation timing.
TCNT Comparematch signal Comparematch buffer signal TGRA, TGRB
n
n+1
n
N
TGRC, TGRD
N
Figure 8.33 Buffer Operation Timing (Compare-Match)
Input capture signal Input capture signal buffer N N+1
TCNT
TGRA, TGRB
n
N
N+1
TGRC, TGRD
n
N
Figure 8.34 Buffer Operation Timing (Input Capture)
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8.6.2
Interrupt Signal Timing
Setting TGF Flag Timing during Compare-Match: Figure 8.35 shows timing for the TGF flag of the timer status register (TSR) due to compare-match, as well as TGI interrupt request signal timing.
TCNT input clock TCNT N N+1
TGR Comparematch signal TGF flag
N
TGI interrupt
Figure 8.35 TGI Interrupt Timing (Compare Match)
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Setting TGF Flag Timing during Input Capture: Figure 8.36 shows timing for the TGF flag of the timer status register (TSR) due to input capture, as well as TGI interrupt request signal timing.
Input capture signal TCNT N
TGR
N
TGF flag
TGI interrupt
Figure 8.36 TGI Interrupt Timing (Input Capture) Setting Timing for Overflow Flag (TCFV): Figure 8.37 shows timing for the TCFV flag of the timer status register (TSR) due to overflow, as well as TCIV interrupt request signal timing.
TCNT input clock TCNT (overflow) Overflow signal TCFV flag H'FFFF H'0000
TCIV interrupt
Figure 8.37 TCIV Interrupt Setting Timing
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Status Flag Clearing Timing: The status flag is cleared when the CPU reads a 1 status followed by a 0 write. Figure 8.38 shows the timing for status flag clearing by the CPU.
TSR write cycle T1 Address T2
TSR address
Write signal
Status flag
Interrupt request signal
Figure 8.38 Timing of Status Flag Clearing by the CPU
8.7
Notes and Precautions
This section describes contention and other matters requiring special attention during MTU operations. Note on Cycle Setting: When setting a counter clearing by compare-match, clearing is done in the final state when TCNT matches the TGR value (update timing for count value on TCNT match). The actual number of states set in the counter is given by the following equation:
f= (N + 1)
(f: counter frequency, : operating frequency, N: value set in the TGR)
Contention between TCNT Write and Clear: If a counter clear signal is issued in the T 2 state during the TCNT write cycle, TCNT clearing has priority, and TCNT write is not conducted (figure 8.39).
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TCNT write cycle T1 Address Write signal Counter clear signal TCNT N H'0000 TCNT address T2
Figure 8.39 TCNT Write and Clear Contention Contention between TCNT Write and Increment: If a count-up signal is issued in the T2 state during the TCNT write cycle, TCNT write has priority, and the counter is not incremented (figure 8.40).
TCNT write cycle T1 T2
Address
TCNT address
Write signal TCNT input clock TCNT N M
TCNT write data
Figure 8.40 TCNT Write and Increment Contention
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Contention between Buffer Register Write and Compare Match: If a compare-match occurs in the T2 state of the TGR write cycle, data is transferred by the buffer operation from the buffer register to the TGR. On channel 0, the data to be transferred is that after the write (figure 8.41).
TGR write cycle T1 Buffer register address T2
Address Write signal Compare match signal Compare match buffer signal
Buffer register write data Buffer register TGR N M M
Figure 8.41 TGR Write and Compare-Match Contention (Channel 0)
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Contention between TGR Read and Input Capture: If an input capture signal is issued in the T1 state of the TGR read cycle, the read data is that after input capture transfer (figure 8.42).
TGR read cycle T1 Address Read signal Input capture signal TGR X M TGR address T2
Internal data bus
M
Figure 8.42 TGR Read and Input Capture Contention
144
Contention between TGR Write and Input Capture: If an input capture signal is issued in the T2 state of the TGR read cycle, input capture has priority, and TGR write does not occur (figure 8.43).
TGR write cycle T1 Address Write signal Input capture signal TCNT TGR M M TGR address T2
Figure 8.43 TGR Write and Input Capture Contention
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Contention between Buffer Register Write and Input Capture: If an input capture signal is issued in the T 2 state of the buffer write cycle, write to the buffer register does not occur, and buffer operation takes priority (figure 8.44).
Buffer register write cycle T1 Address Write signal Input capture signal TCNT TGR Buffer register M N N M Buffer register address T2
Figure 8.44 Buffer Register Write and Input Capture Contention
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Contention Between TGR Write and Compare Match: If a compare-match occurs in the T2 state of the TGR write cycle, data is written to the TGR and a compare-match signal is issued (figure 8.45).
TGR write cycle T1 Address Write signal Compare match signal TCNT TGR N N TGR write data N+1 M TGR address T2
Figure 8.45 TGR Write and Compare Match Contention TCNT2 Write and Overflow Contention in Cascade Connection: With timer counters TCNT1 and TCNT2 in a cascade connection, when a contention occurs during TCNT1 count (during a TCNT2 overflow) in the T 2 state of the TCNT2 write cycle, the write to TCNT2 is conducted, and the TCNT1 count signal is prohibited. At this point, if there is match with TGR1A and the TCNT1 value, a compare signal is issued. When the TCNT1 count clock is selected as the channel 0 input capture source, TGR0A and TGR0C operate as input capture registers. When TGR0C comparematch/input capture is selected as the TGR1B input capture source, TGR1B operates as an input capture register. The timing is shown in figure 8.46. For cascade connections, be sure to synchronize settings for channels 1 and 2 when setting TCNT clearing.
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TCNT write cycle T1 Address Write signal TCNT2 H'FFFE H'FFFF TCNT2 write data TGR2A-B Ch2 comparematch signal A/B TCNT1 input clock TCNT1 TGR1A Ch1 comparematch signal A TGR1B Ch1 inputcapture signal B TCNT0 P N M M M Disabled H'FFFF N N+1 T2
TCNT2 address
TGR0A-D Ch0 input capture signal A, C
Q
P
Figure 8.46 TCNT2 Write and Overflow Contention with Cascade Connection
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Contention between Overflow and Counter Clearing: If overflow and counter clearing occur simultaneously, the TCFV flag in TSR is not set and TCNT clearing takes precedence. Figure 8.47 shows the operation timing when a TGR compare-match is specified as the clearing source, and H'FFFF is set in TGR.
o
TCNT input clock TCNT
H'FFFF
H'0000
Counter clear signal
TGF flag Disabled TCFV flag
Figure 8.47 Contention between Overflow and Counter Clearing Contention between TCNT Write and Overflow: If there is an up-count in the T2 state of a TCNT write cycle, and overflow occurs, the TCNT write takes precedence and the TCFV flag in TSR is not set . Figure 8.48 shows the operation timing in this case.
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TCNT write cycle T1 o T2
Address
TCNT address
Write signal
TCNT input clock
TCNT
H'FFFF
N
TCNT write data
Disabled TCFV flag
Figure 8.48 Contention between TCNT Write and Overflow
8.8
8.8.1
MTU Output Pin Initialization
Operating Modes
The MTU has the following three operating modes. Waveform output is possible in all of these modes. * Normal mode (channels 0 to 2) * PWM mode 1 (channels 0 to 2) * PWM mode 2 (channels 0 to 2) The MTU output pin initialization method for each of these modes is described in this section.
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8.8.2
Reset Start Operation
The MTU output pins (TIOC*) are initialized low by a reset and in standby mode. Since MTU pin function selection is performed by the pin function controller (PFC), when the PFC is set, the MTU pin states at that point are output to the ports. When MTU output is selected by the PFC immediately after a reset, the MTU output initial level, low, is output directly at the port. When the active level is low, the system will operate at this point, and therefore the PFC setting should be made after initialization of the MTU output pins is completed. Note: * represents the channel number and port symbol. 8.8.3 Operation in Case of Re-Setting Due to Error During Operation, Etc.
If an error occurs during MTU operation, MTU output should be cut by the system. Cutoff is performed by switching the pin output to port output with the PFC and outputting the inverse of the active level. The pin initialization procedures for re-setting due to an error during operation, etc., and the procedures for restarting in a different mode after re-setting, are shown below. The MTU has three operating modes, as stated above. There are thus 9 mode transition combinations. Possible mode transition combinations are shown in table 8.9. Table 8.9 Mode Transition Combinations
After Before Normal PWM1 PWM2 Normal (1) (4) (7) PWM1 (2) (5) (8) PWM2 (3) (6) (9)
Legend: Normal: Normal mode PWM1: PWM1 mode PWM2: PWM2 mode The above abbreviations are used in some places in the following descriptions.
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8.8.4
Overview of Initialization Procedures and Mode Transitions in Case of Error During Operation, Etc.
* When making a transition to a mode (Normal, PWM1, PWM2) in which the pin output level is selected by the timer I/O control register (TIOR) setting, initialize the pins by means of a TIOR setting. * In PWM mode 1, since a waveform is not output to the TIOC*B pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 1. * In PWM mode 2, since a waveform is not output to the cycle register pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 2. * In normal mode or PWM mode 2, if TGRC and TGRD operate as buffer registers, setting TIOR will not initialize the buffer register pins. If initialization is required, clear buffer mode, carry out initialization, then set buffer mode again. * In PWM mode 1, if either TGRC or TGRD operates as a buffer register, setting TIOR will not initialize the TGRC pin. To initialize the TGRC pin, clear buffer mode, carry out initialization, then set buffer mode again. Note: An asterisk in this section represents the channel number. Pin initialization procedures are described below for the numbered combinations in table 8.9. The active level is assumed to be low.
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(1) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Normal Mode: Figure 8.49 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in normal mode after re-setting.
1 2 RESET TMDR (normal) 3 4 5 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 6 Match 7 8 9 10 11 12 13 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out)
MTU output TIOC*A TIOC*B Port output PEn PEn n = 0, 2, 4-7, 12-14 Z Z
Figure 8.49 Error Occurrence in Normal Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. After a reset, MTU output is low and ports are in the high-impedance state. After a reset, the TMDR setting is for normal mode. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) Set MTU output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. Not necessary when restarting in normal mode. Initialize the pins with TIOR. Set MTU output with the PFC. Operation is restarted by TSTR.
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(2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 8.50 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 1 after re-setting.
1 2 RESET TMDR (normal) 3 4 5 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 6 Match 7 8 9 10 11 12 13 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out)
MTU output TIOC*A TIOC*B Port output PEn PEn n = 0, 2, 4-7, 12-14 Z Z * Not initialized (TO*B)
Figure 8.50 Error Occurrence in Normal Mode, Recovery in PWM Mode 1 1 to 9 are the same as in figure 8.49. 10. Set PWM mode 1. 11. Initialize the pins with TIOR. (In PWM mode 1, the TO*B side is not initialized. If initialization is required, initialize in normal mode, then switch to PWM mode 1.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR.
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(3) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 2: Figure 8.51 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 2 after re-setting.
1 2 RESET TMDR (normal) 3 4 5 TIOR PFC TSTR ("1"init (MTU) (1) "0"out) 6 Match 7 8 9 10 11 12 13 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM2) (1 init (MTU) (1) 0 out)
MTU output TIOC*A TIOC*B Port output PEn PEn n = 0, 2, 4-7, 12-14 Z Z * Not initialized (cycle register)
Figure 8.51 Error Occurrence in Normal Mode, Recovery in PWM Mode 2 1 to 9 are the same as in figure 8.49. 10. Set PWM mode 2. 11. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized. If initialization is required, initialize in normal mode, then switch to PWM mode 2.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR.
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(4) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Normal Mode: Figure 8.52 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in normal mode after re-setting.
1 2 RESET TMDR (PWM1) 3 4 5 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 6 Match 7 8 9 10 11 12 13 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out)
MTU output TIOC*A TIOC*B Port output PEn PEn n = 0, 2, 4-7, 12-14 Z Z
* Not initialized (TIOC*B)
Figure 8.52 Error Occurrence in PWM Mode 1, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. After a reset, MTU output is low and ports are in the high-impedance state. Set PWM mode 1. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 1, the TIOC*B side is not initialized.) Set MTU output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. Set normal mode. Initialize the pins with TIOR. Set MTU output with the PFC. Operation is restarted by TSTR.
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(5) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 1: Figure 8.53 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re-setting.
1 2 RESET TMDR (PWM1) 3 4 5 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 6 Match 7 8 9 10 11 12 13 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out)
MTU output TIOC*A TIOC*B Port output PEn PEn n = 0, 2, 4-7, 12-14 Z Z * Not initialized (TIOC*B) * Not initialized (TIOC*B)
Figure 8.53 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1 1 to 9 are the same as in figure 8.52. 10. Not necessary when restarting in PWM mode 1. 11. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR.
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(6) Operation when Rrror Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 2: Figure 8.54 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 2 after re-setting.
1 2 RESET TMDR (PWM1) 3 4 5 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 6 Match 7 8 9 10 11 12 13 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM2) (1 init (MTU) (1) 0 out)
MTU output TIOC*A TIOC*B Port output PEn PEn n = 0, 2, 4-7, 12-14 Z Z * Not initialized (TIOC*B) * Not initialized (cycle register)
Figure 8.54 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2 1 to 9 are the same as in figure 8.52. 10. Set PWM mode 2. 11. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR.
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(7) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Normal Mode: Figure 8.55 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting.
1 2 3 RESET TMDR TIOR (PWM2) (1 init 0 out) 4 5 6 7 8 9 10 11 12 13 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (MTU) (1) occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out)
MTU output TIOC*A TIOC*B Port output PEn PEn n = 0, 2, 4-7, 12-14 Z Z * Not initialized (cycle register)
Figure 8.55 Error Occurrence in PWM Mode 2, Recovery in Normal Mode 1. 2. 3. After a reset, MTU output is low and ports are in the high-impedance state. Set PWM mode 2. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 2, the cycle register pins are not initialized. In the example, TIOC*A is the cycle register.) Set MTU output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. Set normal mode. Initialize the pins with TIOR. Set MTU output with the PFC. Operation is restarted by TSTR.
4. 5. 6. 7. 8. 9. 10. 11. 12. 13.
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(8) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 1: Figure 8.56 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re-setting.
1 2 3 RESET TMDR TIOR (PWM2) (1 init 0 out) 4 5 6 7 8 9 10 11 12 13 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (MTU) (1) occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out)
MTU output TIOC*A TIOC*B Port output PE* PE* n = 0, 2, 4-7, 12-14 Z Z * Not initialized (cycle register) * Not initialized (TIOC*B)
Figure 8.56 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 1 1 to 9 are the same as in figure 8.55. 10. Set PWM mode 1. 11. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR.
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(9) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 2: Figure 8.57 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 2 after re-setting.
1 2 3 4 5 6 7 8 9 10 11 12 13 RESET TMDR TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (PWM2) (1 init (MTU) (1) occurs (PORT) (0) (PWM2) (1 init (MTU) (1) 0 out) 0 out)
MTU output TIOC*A TIOC*B Port output PEn PEn n = 0, 2, 4-7, 12-14 Z Z * Not initialized (cycle register) * Not initialized (cycle register)
Figure 8.57 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 2 1 to 9 are the same as in figure 8.55. 10. Not necessary when restarting in PWM mode 2. 11. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR.
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Section 9 8-Bit Timer 1 (TIM1)
9.1 Overview
8-bit timer 1 (TIM1) is a single-channel interval timer that generates an interval timer interrupt each time the counter overflows. 9.1.1 Features
* 8-bit interval timer * Generates interval timer interrupts An interval timer interrupt is generated each time the counter overflows. * Selection of eight counter input clock sources
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9.1.2
Block Diagram
Figure 9.1 shows a block diagram of 8-bit timer 1 (TIM1).
ITI (interrupt request signal)
Overflow Interrupt control Clock Clock selection
/2 /64 /128 /256 /512 /1024 /4096 /8192 Internal clock sources
T1CNT
T1CSR
Module bus
Bus interface
8-bit timer 1 T1CSR: Timer 1 control/status register T1CNT: Timer 1 counter
Figure 9.1 Block Diagram of 8-Bit Timer 1
164
Internal bus
9.1.3
Register Configuration
8-bit timer 1 (TIM1) has two registers, as shown in table 9.1. These registers perform clock selection and other functions. Table 9.1 8-Bit Timer 1 Registers
Address Name Timer 1 control/ status register Timer 1 counter Abbreviation T1CSR T1CNT R/W R/(W)*3 R/W Initial Value H18 H'00 Write*
1
Read* 2 H'FFFF8610 H'FFFF8611
H'FFFF8610
Notes: 1. Use word-length writes. Byte and longword writes cannot be used. 2. Use byte-length reads. A word or longword read will not return the correct value. 3. Only 0 can be written in bit 7, to clear the flag.
9.2
9.2.1
Register Descriptions
Timer 1 Counter (T1CNT)
The timer 1 counter (T1CNT) is an 8-bit readable/writable* up-counter. When the timer enable bit (TME) is set to 1 in the timer 1 control/status register (T1CSR), T1CNT starts incrementing on the internal clock selected by bits CKS2--CKS0 in T1CSR. When the T1CNT value overflows (from H'FF to H'00), an interval timer interrupt (ITI) is generated. T1CNT is initialized to H'00 by a hardware reset or when the TME bit is 0. Note: The method for writing to T1CNT is different from that for general registers to prevent inadvertent overwriting. For details, see section 9.2.3, Notes on Register Access.
Bit: 7 6 5 4 3 2 1 0
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
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9.2.2
Timer 1 Control/Status Register (T1CSR)
The timer 1 control/status register (T1CSR) is an 8-bit readable/writable* register that selects the clock to be input to the timer 1 counter (T1CNT) and the timer mode. Bits 7, 5, and 2 through 0 are initialized to 0 by a power-on reset. Note: The method for writing to T1CSR is different from that for general registers to prevent inadvertent overwriting. For details, see section 9.2.3, Notes on Register Access.
Bit: 7 OVF Initial value: R/W: 0 R/(W)* 6 -- 0 R 5 TME 0 R/W 4 -- 1 R 3 -- 1 R 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
* Bit 7--Overflow Flag (OVF): Indicates that T1CNT has overflowed from H'FF to H'00.
Bit 7: OVF 0 Description No T1CNT overflow (initial value) [Clearing condition] Cleared by reading OVF then writing 0 in OVF 1 [Setting condition] Set when T1CNT overflows
* Bit 6--Reserved: This bit always reads 0 and must only be written with 0. * Bit 5--Timer Enable (TME): Selects whether TCNT runs or is halted.
Bit 5: TME 0 1 Description Timer disabled: T1CNT is initialized to H'00 and halted (initial value) Timer enabled: T1CNT starts counting, and an interrupt is generated when T1CNT overflows
* Bits 4 and 3--Reserved: These bits always read 1 and must only be written with 1. * Bits 2 to 0--Clock Select 2 to 0 (CKS2-CKS0): These bits select one of eight internal clock sources, obtained by dividing the system clock (), for input to T1CNT.
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Bit 2: CKS2 0
Bit 1: CKS1 0
Bit 0: CKS0 0 1
Description Clock /2 (initial value) /64 /128 /256 /512 /1024 /4096 /8192 Overflow Period* (when = 20.0 MHz) 25.6 s 819.2 s 1.6384 ms 3.2768 ms 6.5536 ms 13.1072 ms 52.4288 ms 104.8576 ms
1
0 1
1
0
0 1
1
0 1
Note: The overflow period is the time from when T1CNT starts counting up from H'00 until overflow occurs.
9.2.3
Notes on Register Access
The method for writing to the timer 1 counter (T1CNT) and the timer 1 control/status register (T1CSR) is different from that for general registers to prevent inadvertent overwriting. The procedures for writing to and reading these registers are given below. Writing to T1CNT and T1CSR: These registers must be written to with a word transfer instruction. They cannot be written to with a byte instruction. T1CNT and T1CSR both have the same write address. For a write to T1CNT, the upper byte of the written word must contain H'5A and the lower byte must contain the write data. For a write to T1CSR, the upper byte of the written word must contain H'A5 and the lower byte must contain the write data. This transfers the write data from the lower byte to T1CNT or T1CSR. (See figure 9.2).
T1CNT write 15 Address: H'FFFF8610 H'5A 87 Write data 0
T1CSR write Address: H'FFFF8610
15 H'A5
87 Write data
0
Figure 9.2 Writing to T1CNT and T1CSR
167
Reading T1CNT and T1CSR: These registers are read in the same way as other registers. The read addresses are H'FFFF8610 for T1CSR and H'FFFF8611 for T1CNT. A byte transfer instruction must be used to read these registers.
9.3
9.3.1
Operation
Interval Timer Operation
To use the interval timer function, set the TME bit to 1 in the timer 1 control/status register (T1CSR). An interval timer interrupt (ITI) is generated each time the timer 1 counter (T1CNT) overflows, as shown in figure 9.3. This function can be used to generate interrupts at regular intervals.
T1CNT value Overflow H'FF Overflow Overflow Overflow
H'00 TME = 1 ITI ITI ITI ITI
Time
ITI: Interval timer interrupt request generation
Figure 9.3 Interval Timer Operation
168
9.3.2
Timing of Overflow Flag (OVF) Setting
When the timer 1 counter (T1CNT) overflows, the OVF bit is set to 1 in the timer 1 serial control register (T1CSR) and, at the same time, an interval timer interrupt (ITI) is requested. The timing is shown in figure 9.4.
CK
T1CNT
H'FF
H'00
Overflow signal (internal signal)
OVF
Figure 9.4 Timing of Overflow Flag (OVF) Setting
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9.4
9.4.1
Usage Notes
Contention between Timer 1 Counter (TCNT) Write and Increment
If a timer 1 counter clock pulse is generated during the T3 state of a timer 1 counter (TCNT) write cycle, the data write to T1CNT takes priority and the timer counter is not incremented. Figure 9.5 shows the operation in this case.
T1CNT write cycle T1 T2 T3
CK
Address
T1CNT address
Internal write signal
T1CNT input clock pulse
T1CNT
N
M Counter write data
Figure 9.5 Contention between T1CNT Write and Increment 9.4.2 Rewriting Bits CKS2 to CKS0
If bits CKS2 to CKS0 in the timer 1 control/status register (T1CSR) are rewritten while 8-bit timer 1 (TIM1) is running, the timer counter may not increment correctly. TIM1 must therefore be stopped (by clearing the TME bit to 0) before rewriting bits CKS2 to CKS0.
170
Section 10 8-Bit Timer 2 (TIM2)
10.1 Overview
8-bit timer 2 (TIM2) is a single-channel interval timer that generates compare match interrupts. 10.1.1 Features
* 8-bit interval timer * Generates compare match interrupts A compare match interrupt is generated by a counter compare match. * Selection of seven counter input clock sources
171
10.1.2
Block Diagram
Figure 10.1 shows a block diagram of 8-bit timer 2 (TIM2).
CMI (interrupt request signal)
Interrupt control Clock Clock selection
/2 /8 /32 /128 /512 /2048 /4096
T2COR
Comparator
T2CNT
T2CSR
Module bus
Bus interface
8-bit timer 2 T2CSR: Timer 2 control/status register T2CNT: Timer 2 counter T2COR: Timer 2 constant register
Figure 10.1 Block Diagram of 8-Bit Timer 2 10.1.3 Register Configuration
8-bit timer 2 (TIM2) has three registers for compare match cycle setting, clock selection, and other functions. The register configuration is shown in table 10.1. All the registers are 16 bits in size, and are initialized by a power-on reset.
172
Internal bus
Table 10.1 8-Bit Timer 2 Registers
Name Timer 2 control/status register Timer 2 counter Timer 2 constant register Abbreviation T2CSR T2CNT T2COR R/W R/W R/W R/W Initial Value H'0000 H'0000 H'0000 Address H'FFFF862C H'FFFF862E H'FFFF8630 Access Size 8, 16, 32 8, 16, 32 8, 16
10.2
10.2.1
Register Descriptions
Timer 2 Control/Status Register (T2CSR)
The timer 2 control/status register (T2CSR) is a 16-bit readable/writable* register that selects the clock to be input to the timer 2 counter (T2CNT) and controls compare match interrupts (CMI). T2CSR is initialized to H'0000 by a power-on reset.
Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 CMF 0 R/W 13 -- 0 R 5 CMIE 0 R/W 12 -- 0 R 4 CKS2 0 R/W 11 -- 0 R 3 CKS1 0 R/W 10 -- 0 R 2 CKS0 0 R/W 9 -- 0 R 1 -- 0 R 8 -- 0 R 0 -- 0 R
* Bits 15 to 7--Reserved: These bits always read 0 and must only be written with 0. * Bit 6--Compare Match Flag (CMF): Status flag that indicates a match between the values of T2CNT and T2COR. The setting and clearing conditions for this flag are shown below.
Bit 6: CMF 0 1 Description [Clearing condition] Cleared by reading T2CSR when CMF = 1, then writing 0 in CMF (initial value) [Setting condition] Set when T2CNT = T2COR*
Note: When T2CNT and T2COR still contain their initial values (when the initial values have not been changed or when the T2CNT value has not been incremented), CMF is not set even though the T2CNT and T2COR values are the same (H'0000). 173
* Bit 5--Compare Match Interrupt Enable (CMIE): Enables or disables interrupt requests initiated by the CMF flag when set to 1 in T2CSR.
Bit 5: CMIE 0 1 Description Interrupt request by CMF flag disabled (initial value) Interrupt request by CMF flag enabled
* Bits 4 to 2--Clock Select 2 to 0 (CKS2-CKS0): These bits select one of seven internal clock sources, obtained by dividing the system clock (), for input to T2CNT.
Bit 4: CKS2 0 Bit 3: CKS1 0 Bit 2: CKS0 0 1 1 0 1 1 0 0 1 1 0 1 Description Up-count stopped (initial value) /2 /8 /32 /128 /512 /2048 /4096
* Bits 1 and 0--Reserved: These bits always read 0 and must only be written with 0. 10.2.2 Timer 2 Counter (T2CNT)
The timer 2 counter (T2CNT) is a 16-bit readable/writable register used as an 8-bit up-counter. T2CNT increments on the internal clock selected by bits CKS2-CKS0 in T2CSR. The T2CNT value can be read or written by the CPU at all times. When the T2CNT value matches the value in the timer 2 constant register (T2COR), T2CNT is cleared to H'0000 and the CMF flag is set to 1 in T2CSR. If the CMIE bit in T2CSR is set to 1 at this time, a compare match interrupt (CMI) is generated. Bits 15 to 8 are reserved and have no counter function. These bits always read 0 and must only be written with 0. T2CNT is initialized to H'0000 by a power-on reset
174
Bit:
15 --
14 -- 0 R 6
13 -- 0 R 5
12 -- 0 R 4
11 -- 0 R 3
10 -- 0 R 2
9 -- 0 R 1
8 -- 0 R 0
Initial value: R/W: Bit:
0 R 7
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
10.2.3
Timer 2 Constant Register (T2COR)
The timer 2 constant register (T2COR) is a 16-bit readable/writable register that is used to set the T2CNT compare match cycle. The values in T2COR and T2CNT are continually compared, and when the values match the CMF flag is set in T2CSR and T2CNT is cleared to 0. If the CMIE bit in T2CSR is set to 1, an interrupt request is sent to the interrupt controller in response to the match signal. The interrupt request is output continuously until the CMF flag in T2CSR is cleared. Bits 15 to 8 are reserved and are not used in the cycle setting. These bits always read 0. T2COR is initialized to H'0000 by a power-on reset.
Bit: 15 -- Initial value: R/W: Bit: 0 R 7 14 -- 0 R 6 13 -- 0 R 5 12 -- 0 R 4 11 -- 0 R 3 10 -- 0 R 2 9 -- 0 R 1 8 -- 0 R 0
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
175
10.3
10.3.1
Operation
Cyclic Count Operation
When a clock is selected with bits CKS2-CKS0 in the T2CSR register, the T2CNT counter starts incrementing on the selected clock. When the T2CNT counter value matches the value in the timer 2 constant register (T2COR), the T2CNT counter is cleared to H'00, and the CMF flag is set to 1 in the T2CSR register. If the CMIE bit in T2CSR is set to 1 at this time, a compare match interrupt (CMI) is requested. The T2CNT counter then starts incrementing again from H'00. The compare match counter operation is shown in figure 10.2.
T2CNT value Counter cleared by T2COR compare match T2COR
H'00
Time
Figure 10.2 Counter Operation 10.3.2 T2CNT Count Timing
Any of seven internal clocks (/2, /8, /32, /128, /512, /2048, or /4096) divided from the system clock (CK) can be selected with bits CKS2-CKS0 in T2CSR. The count timing is shown in figure 10.3.
CK Internal clock T2CNT input clock T2CNT N-1 N N+1
Figure 10.3 Count Timing
176
10.4
10.4.1
Interrupts
Interrupt Source
When interrupt request flag CMF is set to 1, and interrupt enable bit CMIE is also 1, the corresponding interrupt request is output. 10.4.2 Timing of Compare Match Flag Setting
The CMF bit in the T2CSR register is set to 1 by the compare match signal generated when the T2COR register and T2CNT counter values match. The compare match signal is generated in the last state in which the match is true (when the value at which the T2CNT counter match occurred is about to be updated). Therefore, after a match between the T2CNT counter and the T2COR register, the compare match signal is not generated until the next T2CNT counter input clock pulse. Figure 10.4 shows the timing of CMF bit setting.
CK T2CNT input clock pulse T2CNT T2COR Compare match signal CMF CMI N N 0
Figure 10.4 Timing of CMF Setting
177
10.4.3
Timing of Compare Match Flag Clearing
The CMF bit in the T2CSR register is cleared by reading the bit when it is set to 1, then writing 0 in it. Figure 10.5 shows the timing of CMF bit clearing by the CPU.
T2CSR write cycle T1 CK CMF T2
Figure 10.5 Timing of CMF Clearing by CPU
178
Section 11 Compare Match Timer (CMT)
11.1 Overview
The SH7011 has an on-chip compare match timer (CMT) configured of 16-bit timers for two channels. The CMT has 16-bit counters and can generate interrupts at set intervals. 11.1.1 Features
The CMT has the following features: * Four types of counter input clock can be selected One of four internal clocks (/8, /32, /128, /512) can be selected independently for each channel. * Interrupt sources A compare match interrupt can be requested independently for each channel.
179
11.1.2
Block Diagram
Figure 11.1 shows a block diagram of the CMT.
CM10 /8 /32 /128 /512 CMI1 /8 /32 /128 /512
Control circuit
Clock selection
Control circuit
Clock selection
Comparator
Comparator
CMCOR0
CMCOR1
CMCSR0
CMCSR1
CMCNT0
CMCNT1 Bus interface Internal bus
CMSTR
Module bus CMT CMSTR: CMCSR: CMCOR: CMCNT: CMI: Compare match timer start register Compare match timer control/status register Compare match timer constant register Compare match timer counter Compare match interrupt
Figure 11.1 CMT Block Diagram
180
11.1.3
Register Configuration
Table 11.1 summarizes the CMT register configuration. Table 11.1 Register Configuration
Channel Name Shared 0 Abbreviation R/W R/W R/(W)* R/W R/W R/(W)* R/W R/W Initial Value H'0000 H'0000 H'0000 Address Access Size (Bits)
Compare match timer CMSTR start register Compare match timer CMCSR0 control/status register 0 Compare match timer CMCNT0 counter 0 Compare match timer CMCOR0 constant register 0
H'FFFF83D0 8, 16, 32 H'FFFF83D2 8, 16, 32 H'FFFF83D4 8, 16, 32
H'FFFF H'FFFF83D6 8, 16, 32 H'0000 H'0000 H'FFFF83D8 8, 16, 32 H'FFFF83DA 8, 16, 32
1
Compare match timer CMCSR1 control/status register 1 Compare match timer CMCNT1 counter 1 Compare match timer CMCOR1 constant register 1
H'FFFF H'FFFF83DC 8, 16
Note: The only value that can be written to the CMCSR0 and CMCSR1 CMF bits is a 0 to clear the flags.
181
11.2
11.2.1
Register Descriptions
Compare Match Timer Start Register (CMSTR)
The compare match timer start register (CMSTR) is a 16-bit register that selects whether to operate or halt the channel 0 and channel 1 counters (CMCNT). It is initialized to H'0000 by power-on resets.
Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 STR1 0 R/W 8 -- 0 R 0 STR0 0 R/W
* Bits 15-2--Reserved: These bits always read as 0. The write value should always be 0. * Bit 1--Count Start 1 (STR1): Selects whether to operate or halt compare match timer counter 1.
Bit 1: STR1 0 1 Description CMCNT1 count operation halted (initial value) CMCNT1 count operation
* Bit 0--Count Start 0 (STR0): Selects whether to operate or halt compare match timer counter 0.
Bit 0: STR0 0 1 Description CMCNT0 count operation halted (initial value) CMCNT0 count operation
182
11.2.2
Compare Match Timer Control/Status Register (CMCSR)
The compare match timer control/status register (CMCSR) is a 16-bit register that indicates the occurrence of compare matches, sets the enable/disable of interrupts, and establishes the clock used for incrementation. It is initialized to H'0000 by power-on resets.
Bit: 15 -- Initial value: R/W: Bit: 0 R 7 CMF Initial value: R/W: 0 R/(W)* 14 -- 0 R 6 CMIE 0 R/W 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 -- 0 R 9 -- 0 R 1 CKS1 0 R/W 8 -- 0 R 0 CKS0 0 R/W
Note: The only value that can be written is a 0 to clear the flag.
* Bits 15-8 and 5-2--Reserved: These bits always read as 0. The write value should always be 0. * Bit 7--Compare Match Flag (CMF): This flag indicates whether or not the CMCNT and CMCOR values have matched.
Bit 7: CMF 0 Description CMCNT and CMCOR values have not matched (initial status) Clear condition: Write a 0 to CMF after reading a 1 from it 1 CMCNT and CMCOR values have matched
* Bit 6--Compare Match Interrupt Enable (CMIE): Selects whether to enable or disable a compare match interrupt (CMI) when the CMCNT and CMCOR values have matched (CMF = 1).
Bit 6: CMIE 0 1 Description Compare match interrupts (CMI) disabled (initial status) Compare match interrupts (CMI) enabled
183
* Bits 1, 0--Clock Select 1, 0 (CKS1, CKS0): These bits select the clock input to the CMCNT from among the four internal clocks obtained by dividing the system clock (). When the STR bit of the CMSTR is set to 1, the CMCNT begins incrementing with the clock selected by CKS1 and CKS0.
Bit 1: CKS1 0 Bit 0: CKS0 0 1 1 0 1 Description /8 (initial status) /32 /128 /512
11.2.3
Compare Match Timer Counter (CMCNT)
The compare match timer counter (CMCNT) is a 16-bit register used as an upcounter for generating interrupt requests. When an internal clock is selected with the CKS1, CKS0 bits of the CMCSR register and the STR bit of the CMSTR is set to 1, the CMCNT begins incrementing with that clock. When the CMCNT value matches that of the compare match timer constant register (CMCOR), the CMCNT is cleared to H'0000 and the CMF flag of the CMCSR is set to 1. If the CMIE bit of the CMCSR is set to 1 at this time, a compare match interrupt (CMI) is requested. The CMCNT is initialized to H'0000 by power-on resets.
Bit: 15 14 13 12 11 10 9 8
Initial value: R/W: Bit:
0 R/W 7
0 R/W 6
0 R/W 5
0 R/W 4
0 R/W 3
0 R/W 2
0 R/W 1
0 R/W 0
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
184
11.2.4
Compare Match Timer Constant Register (CMCOR)
The compare match timer constant register (CMCOR) is a 16-bit register that sets the compare match period with the CMCNT. The CMCOR is initialized to H'FFFF by power-on resets.
Bit: 15 14 13 12 11 10 9 8
Initial value: R/W: Bit:
1 R/W 7
1 R/W 6
1 R/W 5
1 R/W 4
1 R/W 3
1 R/W 2
1 R/W 1
1 R/W 0
Initial value: R/W:
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
11.3
11.3.1
Operation
Period Count Operation
When an internal clock is selected with the CKS1, CKS0 bits of the CMCSR register and the STR bit of the CMSTR is set to 1, the CMCNT begins incrementing with the selected clock. When the CMCNT counter value matches that of the compare match constant register (CMCOR), the CMCNT counter is cleared to H'0000 and the CMF flag of the CMCSR register is set to 1. If the CMIE bit of the CMCSR register is set to 1 at this time, a compare match interrupt (CMI) is requested. The CMCNT counter begins counting up again from H'0000. Figure 11.2 shows the compare match counter operation.
CMCNT value CMCOR
Counter cleared by CMCOR compare match
H'0000
Time
Figure 11.2 Counter Operation
185
11.3.2
CMCNT Count Timing
One of four clocks (/8, /32, /128, /512) obtained by dividing the system clock (CK) can be selected by the CKS1, CKS0 bits of the CMCSR. Figure 11.3 shows the timing.
CK Internal clock CMCNT input clock CMCNT N-1 N N+1
Figure 11.3 Count Timing
11.4
11.4.1
Interrupts
Interrupt Sources
The CMT has a compare match interrupt for each channel, with independent vector addresses allocated to each of them. The corresponding interrupt request is output when the interrupt request flag CMF is set to 1 and the interrupt enable bit CMIE has also been set to 1. When activating CPU interrupts by interrupt request, the priority between the channels can be changed by using the interrupt controller settings. See section 6, Interrupt Controller, for details. 11.4.2 Compare Match Flag Set Timing
The CMF bit of the CMCSR register is set to 1 by the compare match signal generated when the CMCOR register and the CMCNT counter match. The compare match signal is generated upon the final state of the match (timing at which the CMCNT counter matching count value is updated). Consequently, after the CMCOR register and the CMCNT counter match, a compare match signal will not be generated until a CMCNT counter input clock occurs. Figure 11.4 shows the CMF bit set timing.
186
CK
CMCNT input clock
CMCNT
N
0
CMCOR
N
Compare match signal
CMF
CMI
Figure 11.4 CMF Set Timing 11.4.3 Compare Match Flag Clear Timing
The CMF bit of the CMCSR register is cleared either by writing a 0 to it after reading a 1. Figure 11.5 shows the timing when the CMF bit is cleared by the CPU.
CMCSR write cycle T1 CK T2
CMF
Figure 11.5 Timing of CMF Clear by the CPU
187
11.5
Notes on Use
Take care that the contentions described in sections 11.5.1-11.5.3 do not arise during CMT operation. 11.5.1 Contention between CMCNT Write and Compare Match
If a compare match signal is generated during the T2 state of the CMCNT counter write cycle, the CMCNT counter clear has priority, so the write to the CMCNT counter is not performed. Figure 11.6 shows the timing.
CMCNT write cycle T1 T2
CK
Address
CMCNT
Internal write signal Compare match signal
CMCNT
N
H'0000
Figure 11.6 CMCNT Write and Compare Match Contention
188
11.5.2
Contention between CMCNT Word Write and Incrementation
If an increment occurs during the T 2 state of the CMCNT counter word write cycle, the counter write has priority, so no increment occurs. Figure 11.7 shows the timing.
CMCNT write cycle T1 T2
CK
Address
CMCNT
Internal write signal Compare match signal
CMCNT
N
M CMCNT write data
Figure 11.7 CMCNT Word Write and Increment Contention
189
11.5.3
Contention between CMCNT Byte Write and Incrementation
If an increment occurs during the T 2 state of the CMCNT byte write cycle, the counter write has priority, so no increment of the write data results on the writing side. The byte data on the side not performing the writing is also not incremented, so the contents are those before the write. Figure 11.8 shows the timing when an increment occurs during the T2 state of the CMCNTH write cycle.
CMCNT write cycle T1 CK T2
Address
CMCNTH
Internal write signal CMCNT input clock
CMCNTH
N
M CMCNTH write data
CMCNTL
X
X
Figure 11.8 CMCNT Byte Write and Increment Contention
190
Section 12 Serial Communication Interface (SCI)
12.1 Overview
The SH7011 has a serial communication interface (SCI) with one channel. The SCI supports asynchronous serial communication. It also has a multiprocessor communication function for serial communication among two or more processors. 12.1.1 Features
* Select asynchronous or clock synchronous as the serial communications mode. Asynchronous mode: Serial data communications are synched by start-stop in character units. The SCI can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other chip that employs a standard asynchronous serial communication. It can also communicate with two or more other processors using the multiprocessor communication function. There are twelve selectable serial data communication formats. Data length: seven or eight bits Stop bit length: one or two bits Parity: even, odd, or none Multiprocessor bit: one or none Receive error detection: parity, overrun, and framing errors Break detection: by reading the RxD level directly when a framing error occurs * Full duplex communication: The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. Both sections use double buffering, so continuous data transfer is possible in both the transmit and receive directions. * On-chip baud rate generator with selectable bit rates. * Internal transmit/receive clock source: baud rate generator (internal). * Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receiveerror interrupts are requested independently.
191
12.1.2
Block Diagram
Figure 12.1 shows a block diagram of the SCI.
Bus interface
Module data bus
Internal data bus
RDR
TDR
SSR SCR
BRR /4 /16 /64
RxD
RSR
TSR
SMR Transmit/ receive control
Baud rate generator
TxD Parity generation Parity check
Clock
TEI TxI RxI ERI SCI RSR : RDR: TSR : TDR : Receive shift register Receive data register Transmit shift register Transmit data register SMR : SCR : SSR : BRR : Serial mode register Serial control register Serial status register Bit rate register
Figure 12.1 SCI Block Diagram 12.1.3 Pin Configuration
Table 12.1 summarizes the SCI pins by channel. Table 12.1 SCI Pins
Pin Name Receive data pin Transmit data pin Abbreviation RxD TxD Input/Output Input Output Function SCI receive data input SCI transmit data output
192
12.1.4
Register Configuration
Table 12.2 summarizes the SCI internal registers. These registers specify the data format and bit rate, and control the transmitter and receiver sections. Table 12.2 Registers
Name Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Abbreviation SMR BRR SCR TDR SSR RDR R/W R/W R/W R/W R/W R/(W)* R Initial Value H'00 H'FF H'00 H'FF H'84 H'00 Address H'FFFF81B0 H'FFFF81B1 H'FFFF81B2 H'FFFF81B3 H'FFFF81B4 H'FFFF81B5 Access Size 8, 16 8, 16 8, 16 8, 16 8, 16 8, 16
Note: The only value that can be written is a 0 to clear the flags..
12.2
12.2.1
Register Descriptions
Receive Shift Register (RSR)
The receive shift register (RSR) receives serial data. Data input at the RxD pin is loaded into the RSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to the RDR. The CPU cannot read or write the RSR directly.
Bit: 7 6 5 4 3 2 1 0
R/W:
--
--
--
--
--
--
--
--
193
12.2.2
Receive Data Register (RDR)
The receive data register (RDR) stores serial receive data. The SCI completes the reception of one byte of serial data by moving the received data from the receive shift register (RSR) into the RDR for storage. The RSR is then ready to receive the next data. This double buffering allows the SCI to receive data continuously. The CPU can read but not write the RDR. The RDR is initialized to H'00 by a power-on reset.
Bit: 7 6 5 4 3 2 1 0
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
12.2.3
Transmit Shift Register (TSR)
The transmit shift register (TSR) transmits serial data. The SCI loads transmit data from the transmit data register (TDR) into the TSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data from the TDR into the TSR and starts transmitting again. If the TDRE bit of the SSR is 1, however, the SCI does not load the TDR contents into the TSR. The CPU cannot read or write the TSR directly.
Bit: 7 6 5 4 3 2 1 0
R/W:
--
--
--
--
--
--
--
--
12.2.4
Transmit Data Register (TDR)
The transmit data register (TDR) is an 8-bit register that stores data for serial transmission. When the SCI detects that the transmit shift register (TSR) is empty, it moves transmit data written in the TDR into the TSR and starts serial transmission. Continuous serial transmission is possible by writing the next transmit data in the TDR during serial transmission from the TSR. The CPU can always read and write the TDR. The TDR is initialized to H'FF by a power-on reset.
194
Bit:
7
6
5
4
3
2
1
0
Initial value: R/W:
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
12.2.5
Serial Mode Register (SMR)
The serial mode register (SMR) is an 8-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write the SMR. The SMR is initialized to H'00 by a power-on reset.
Bit: 7 -- Initial value: R/W: 0 R 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
* Bit 7--Reserved. This bit always reads 0. The write value should always be 0. * Bit 6--Character Length (CHR): Selects 7-bit or 8-bit data in the asynchronous mode.
Bit 6: CHR 0 1 Description Eight-bit data (initial value) Seven-bit data. (When 7-bit data is selected, the MSB (bit 7) of the transmit data register is not transmitted.)
* Bit 5--Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the parity of receive data.
Bit 5: PE 0 1 Description Parity bit not added or checked (initial value) Parity bit added and checked. When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting.
195
* Bit 4--Parity Mode (O/E): Selects even or odd parity when parity bits are added and checked. The O/E setting is used only when the parity enable bit (PE) is set to 1 to enable parity addition and check. The O/E setting is ignored when parity addition and check is disabled.
Bit 4: O/E 0 Description Even parity (initial value). If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. Odd parity. If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined.
1
* Bit 3--Stop Bit Length (STOP): Selects one or two bits as the stop bit length. In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character.
Bit 3: STOP 0 1 Description One stop bit (initial value). In transmitting, a single bit of 1 is added at the end of each transmitted character. Two stop bits. In transmitting, two bits of 1 are added at the end of each transmitted character.
* Bit 2--Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format is selected, settings of the parity enable (PE) and parity mode (O/E) bits are ignored. For the multiprocessor communication function, see section 12.3.3, Multiprocessor Communication.
Bit 2: MP 0 1 Description Multiprocessor function disabled (initial value) Multiprocessor format selected
* Bits 1 and 0--Clock Select 1 and 0 (CKS1 and CKS0): These bits select the internal clock source of the on-chip baud rate generator. Four clock sources are available; , /4, /16, or /64. For further information on the clock source, bit rate register settings, and baud rate, see section 12.2.8, Bit Rate Register.
196
Bit 1: CKS1 0
Bit 0: CKS0 0 1
Description (initial value) /4 /16 /64
1
0 1
12.2.6
Serial Control Register (SCR)
The serial control register (SCR) operates the SCI transmitter/receiver, enables/disables interrupt requests. The CPU can always read and write the SCR. The SCR is initialized to H'00 by a poweron reset.
Bit: 7 TIE Initial value: R/W: 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 -- 0 R 0 -- 0 R
* Bit 7--Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt (TxI) requested when the transmit data register empty bit (TDRE) in the serial status register (SSR) is set to 1 by transfer of serial transmit data from the TDR to the TSR.
Bit 7: TIE 0 Description Transmit-data-empty interrupt request (TxI) is disabled (initial value). The TxI interrupt request can be cleared by reading TDRE after it has been set to 1, then clearing TDRE to 0, or by clearing TIE to 0. Transmit-data-empty interrupt request (TxI) is enabled
1
* Bit 6--Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RxI) requested when the receive data register full bit (RDRF) in the serial status register (SSR) is set to 1 by transfer of serial receive data from the RSR to the RDR. It also enables or disables receive-error interrupt (ERI) requests.
Bit 6: RIE 0 Description Receive-data-full interrupt (RxI) and receive-error interrupt (ERI) requests are disabled (initial value). RxI and ERI interrupt requests can be cleared by reading the RDRF flag or error flag (FER, PER, or ORER) after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0. Receive-data-full interrupt (RxI) and receive-error interrupt (ERI) requests are enabled. 197
1
* Bit 5--Transmit Enable (TE): Enables or disables the SCI serial transmitter.
Bit 5: TE 0 1 Description Transmitter disabled (initial value). The transmit data register empty bit (TDRE) in the serial status register (SSR) is locked at 1. Transmitter enabled. Serial transmission starts when the transmit data register empty (TDRE) bit in the serial status register (SSR) is cleared to 0 after writing of transmit data into the TDR. Select the transmit format in the SMR before setting TE to 1.
* Bit 4--Receive Enable (RE): Enables or disables the SCI serial receiver.
Bit 4: RE 0 Description Receiver disabled (initial value). Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, ORER). These flags retain their previous values. Receiver enabled. Serial reception starts when a start bit is detected in the asynchronous mode, or synchronous clock input is detected in the clock synchronous mode. Select the receive format in the SMR before setting RE to 1.
1
* Bit 3--Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE setting is used only if the multiprocessor mode bit (MP) in the serial mode register (SMR) is set to 1 during reception.
Bit 3: MPIE 0 Description Multiprocessor interrupts are disabled (normal receive operation) (initial value). MPIE is cleared when the MPIE bit is cleared to 0, or the multiprocessor bit (MPB) is set to 1 in receive data. Multiprocessor interrupts are enabled. Receive-data-full interrupt requests (RxI), receive-error interrupt requests (ERI), and setting of the RDRF, FER, and ORER status flags in the serial status register (SSR) are disabled until data with the multiprocessor bit set to 1 is received. The SCI does not transfer receive data from the RSR to the RDR, does not detect receive errors, and does not set the RDRF, FER, and ORER flags in the serial status register (SSR). When it receives data that includes MPB = 1, MPB is set to 1, and the SCI automatically clears MPIE to 0, generates RxI and ERI interrupts (if the TIE and RIE bits in the SCR are set to 1), and allows the FER and ORER bits to be set.
1
198
* Bit 2--Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt (TEI) requested if TDR does not contain valid transmit data when the MSB is transmitted.
Bit 2: TEIE 0 1 Description Transmit-end interrupt (TEI) requests are disabled* (initial value) Transmit-end interrupt (TEI) requests are enabled.*
Note: The TEI request can be cleared by reading the TDRE bit in the serial status register (SSR) after it has been set to 1, then clearing TDRE to 0 and clearing the transmit end (TEND) bit to 0; or by clearing the TEIE bit to 0.
* Bits 1 and 0--Reserved. These bits always read 0. The write value should always be 0. 12.2.7 Serial Status Register (SSR)
The serial status register (SSR) is an 8-bit register containing multiprocessor bit values, and status flags that indicate SCI operating status. The CPU can always read and write the SSR, but cannot write 1 in the status flags (TDRE, RDRF, ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. The SSR is initialized to H'84 by a power-on reset.
Bit: 7 TDRE Initial value: R/W: 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W
Note: The only value that can be written is a 0 to clear the flag.
* Bit 7--Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data from the TDR into the TSR and new serial transmit data can be written in the TDR.
Bit 7: TDRE 0 Description TDR contains valid transmit data TDRE is cleared to 0 when software reads TDRE after it has been set to 1, then writes 0 in TDRE 1 TDR does not contain valid transmit data (initial value) TDRE is set to 1 when the chip is power-on reset the TE bit in the serial control register (SCR) is cleared to 0, or TDR contents are loaded into TSR, so new data can be written in TDR
199
* Bit 6--Receive Data Register Full (RDRF): Indicates that RDR contains received data.
Bit 6: RDRF 0 Description RDR does not contain valid received data (initial value) RDRF is cleared to 0 when the chip is power-on reset, software reads RDRF after it has been set to 1, then writes 0 in RDRF 1 RDR contains valid received data RDRF is set to 1 when serial data is received normally and transferred from RSR to RDR Note: The RDR and RDRF are not affected by detection of receive errors or by clearing of the RE bit to 0 in the serial control register. They retain their previous contents. If RDRF is still set to 1 when reception of the next data ends, an overrun error (ORER) occurs and the received data is lost.
* Bit 5--Overrun Error (ORER): Indicates that data reception ended abnormally due to an overrun error.
Bit 5: ORER 0 Description Receiving is in progress or has ended normally (initial value). Clearing the RE bit to 0 in the serial control register does not affect the ORER bit, which retains its previous value. ORER is cleared to 0 when the chip is power-on reset or software reads ORER after it has been set to 1, then writes 0 in ORER 1 A receive overrun error occurred. RDR continues to hold the data received before the overrun error, so subsequent receive data is lost. Serial receiving cannot continue while ORER is set to 1. ORER is set to 1 if reception of the next serial data ends when RDRF is set to 1
200
* Bit 4--Framing Error (FER): Indicates that data reception ended abnormally due to a framing error.
Bit 4: FER 0 Description Receiving is in progress or has ended normally (initial value). Clearing the RE bit to 0 in the serial control register does not affect the FER bit, which retains its previous value. FER is cleared to 0 when the chip is power-on reset or software reads FER after it has been set to 1, then writes 0 in FER 1 A receive framing error occurred. When the stop bit length is two bits, only the first bit is checked to see if it is a 1. The second stop bit is not checked. When a framing error occurs, the SCI transfers the receive data into the RDR but does not set RDRF. Serial receiving cannot continue while FER is set to 1. FER is set to 1 if the stop bit at the end of receive data is checked and found to be 0
* Bit 3--Parity Error (PER): Indicates that data reception (with parity) ended abnormally due to a parity error.
Bit 3: PER 0 Description Receiving is in progress or has ended normally (initial value). Clearing the RE bit to 0 in the serial control register does not affect the PER bit, which retains its previous value. PER is cleared to 0 when the chip is power-on reset or software reads PER after it has been set to 1, then writes 0 in PER 1 A receive parity error occurred. When a parity error occurs, the SCI transfers the receive data into the RDR but does not set RDRF. Serial receiving cannot continue while PER is set to 1. PER is set to 1 if the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of the parity mode bit (O/E) in the serial mode register (SMR)
201
* Bit 2--Transmit End (TEND): Indicates that when the last bit of a serial character was transmitted, the TDR did not contain valid data, so transmission has ended. TEND is a readonly bit and cannot be written.
Bit 2: TEND 0 Description Transmission is in progress TEND is cleared to 0 when software reads TDRE after it has been set to 1, then writes 0 in TDRE 1 End of transmission (initial value) TEND is set to 1 when the chip is power-on reset, TE is cleared to 0 in the serial control register (SCR), or TDRE is 1 when the last bit of a one-byte serial character is transmitted.
* Bit 1--Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data when a multiprocessor format is selected for receiving. The MPB is a read-only bit and cannot be written.
Bit 1: MPB 0 1 Description Multiprocessor bit value in receive data is 0 (initial value). If RE is cleared to 0 when a multiprocessor format is selected, the MPB retains its previous value. Multiprocessor bit value in receive data is 1
* Bit 0--Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to transmit data when a multiprocessor format is selected for transmitting.
Bit 0: MPBT 0 1 Description Multiprocessor bit value in transmit data is 0 (initial value) Multiprocessor bit value in transmit data is 1
202
12.2.8
Bit Rate Register (BRR)
The bit rate register (BRR) is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SMR), determines the serial transmit/receive bit rate. The CPU can always read and write the BRR. The BRR is initialized to H'FF by a power-on reset.
Bit: 7 6 5 4 3 2 1 0
Initial value: R/W:
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Table 12.3 lists examples of BRR settings in the asynchronous mode. Table 12.3 Bit Rates and BRR Settings
(MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 4 n 2 1 1 0 0 0 0 0 0 0 0 0 0 N 70 207 103 207 103 51 25 12 8 6 3 3 2 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -3.55 -6.99 8.51 0.00 8.51 n 2 1 1 0 0 0 0 0 0 0 0 0 0 N 86 255 127 255 127 63 31 15 10 7 4 4 3 4.9152 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -3.03 0.00 6.67 -1.70 0.00 n 2 2 1 1 0 0 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 12 9 6 5 4 6 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.16 -2.34 -6.99 0.00 -2.34
203
Table 12.3 Bit Rates and BRR Settings (cont)
(MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 7.3728 n 2 2 1 1 0 0 0 0 0 0 0 0 0 N 130 95 191 95 191 95 47 23 15 11 7 6 5 Error (%) -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 5.33 0.00 n 2 2 1 1 0 0 0 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 16 12 8 7 6 8 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 2.12 0.16 -3.55 0.00 -6.99 n 2 2 1 1 0 0 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 20 15 10 9 7 9.8304 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.59 0.00 -3.03 -1.70 0.00
204
Table 12.3 Bit Rates and BRR Settings (cont)
(MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 10 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 21 15 10 9 7 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 -1.36 1.73 -1.36 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 195 143 71 143 71 143 71 35 23 17 11 10 8 11.0592 Error (%) 0.19 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.54 0.00 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 25 19 12 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.16 0.00 -2.34
205
Table 12.3 Bit Rates and BRR Settings (cont)
(MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 12.288 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 217 159 79 159 79 159 79 39 26 19 12 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.23 0.00 2.56 2.40 0.00 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 248 181 90 181 90 181 90 45 29 22 14 13 10 14 Error (%) -0.17 0.16 0.16 0.16 0.16 0.16 0.16 -0.93 1.27 -0.93 1.27 0.00 3.57 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 64 191 95 191 95 191 95 47 31 23 15 14 11 14.7456 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00
206
Table 12.3 Bit Rates and BRR Settings (cont)
(MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 16 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 34 25 16 15 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -0.79 0.16 2.12 0.00 0.16 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 75 223 111 223 111 223 111 55 36 27 18 16 13 17.2032 Error (%) 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.90 0.00 -1.75 1.20 0.00 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 79 233 116 233 116 233 116 58 38 28 19 17 14 18 Error (%) -0.12 0.16 0.16 0.16 0.16 0.16 0.16 -0.69 0.16 1.02 -2.34 0.00 -2.34
207
Table 12.3 Bit Rates and BRR Settings (cont)
(MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 18.432 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 81 239 119 239 119 239 119 59 39 29 19 17 14 Error (%) -0.22 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 255 127 63 42 31 20 19 15 19.6608 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -0.78 0.00 1.59 -1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 129 64 42 32 21 19 15 20 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.94 -1.36 -1.36 0.00 1.73
208
The BRR setting is calculated as follows:
N=
64 x 22n-1 x B
x 106 - 1
B: Bit rate (bit/s) N: Baud rate generator BRR setting (0 N 255) : Operating frequency (MHz) n: Baud rate generator input clock (n = 0 to 3) (See the following table for the clock sources and value of n.) SMR Settings n 0 1 2 3 Clock CKS1 0 0 1 1 CKS2 0 1 0 1
/4 /16 /64
The bit rate error in asynchronous mode is calculated as follows:
Error (%) =
x 106
(N + 1) x B x 64 x 22n-1
- 1 x 100
209
Table 12.4 shows the maximum bit rates for various frequencies. Table 12.4 Maximum Bit Rates for Various Frequencies with Baud Rate Generator
Settings (MHz) 4 4.9152 6 7.3728 8 9.8304 10 11.0592 12 12.288 14 14.7456 16 17.2032 18 18.432 19.6608 20 Maximum Bit Rate (Bits/s) 125000 153600 187500 230400 250000 307200 312500 345600 375000 384000 437500 460800 500000 537600 562500 576000 614400 625000 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
210
12.3
12.3.1
Operation
Overview
The SCI can perform serial communication in asynchronous mode, in which characters are synchronized individually. The asynchronous mode transmission format is selected in the serial mode register (SMR), as shown in table 12.5. Asynchronous Mode: * Data length is selectable: seven or eight bits. * Parity and multiprocessor bits are selectable, as well as the stop bit length (one or two bits). These selections determine the transmit/receive format and character length. * In receiving, it is possible to detect framing errors (FER), parity errors (PER), overrun errors (ORER), and the break state. * SCI clock source: internal clock The SCI operates using the on-chip baud rate generator. Table 12.5 Serial Mode Register Settings and SCI Communication Formats
SMR Settings Mode Asynchronous Bit 6 CHR 0 Bit 5 PE Bit 2 MP 0 0 Bit 3 STOP 0 1 1 0 1 1 0 0 1 1 0 1 Asynchronous (multiprocessor format) 0 * * 1 * * 1 0 1 0 1 7-bit 8-bit Not set Set Set 7-bit Not set Set SCI Communication Format Data Length 8-bit Parity Bit Not set Multipro- Stop Bit cessor Bit Length Not set 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits
Note: Asterisks (*) in the table indicate don't-care bits.
211
12.3.2
Operation in Asynchronous Mode
In the asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible. The transmitter and receiver are both double buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. Figure 12.2 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the marking (high) state. The SCI monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in the asynchronous mode, the SCI synchronizes on the falling edge of the start bit. The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit.
Idling (marking state) 1 (MSB) D1 D2 D3 D4 D5 D6 D7 0/1 Parity bit Transmit/receive data 1 bit 7 or 8 bits 1 or no bit 1 or 2 bits 1 1 Stop bit
1 Serial data 0 Start bit
(LSB) D0
One unit of communication data (characters or frames)
Figure 12.2 Data Format in Asynchronous Communication (Example: 8-bit Data with Parity and Two Stop Bits)
212
Transmit/Receive Formats: Table 12.6 shows the 12 communication formats that can be selected in the asynchronous mode. The format is selected by settings in the serial mode register (SMR). Table 12.6 Serial Communication Formats (Asynchronous Mode)
SMR Bits Bit 6: Bit 2: Bit 5: Bit 3: CHR MP PE STOP 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 -- -- -- -- 0 1 0 1 0 1 0 1 0 1 0 1 1 Serial Transmit/Receive Format and Frame Length 2 3 4 5 6 7 8 9 10 11 12
START START START START START START START START START START START START
8-Bit data 8-Bit data 8-Bit data 8-Bit data 7-Bit data 7-Bit data 7-Bit data 7-Bit data 8-Bit data 8-Bit data 7-Bit data 7-Bit data MPB MPB STOP
STOP STOP STOP P P STOP STOP STOP
STOP STOP P P STOP STOP STOP MPB MPB STOP STOP STOP STOP STOP STOP
--: Don't care bits. Note: START: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit
213
Clock: The SCI's transmit/receive clock is an internal clock generated by the on-chip baud rate generator. SCI Initialization (Asynchronous Mode): Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCR), then initialize the SCI as follows. When changing the operation mode or communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (RDR), which retain their previous contents. Figure 12.3 is a sample flowchart for initializing the SCI. The procedure is as follows (the steps correspond to the numbers in the flowchart): 1. Select the clock source in the serial control register (SCR). Leave RIE, TIE, TEIE, MPIE, TE and RE cleared to 0. 2. Select the communication format in the serial mode register (SMR). 3. Write the value corresponding to the bit rate in the bit rate register (BRR). 4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCR) to 1. Also set RIE, TIE, TEIE and MPIE as necessary. Setting TE or RE enables the SCI to use the TxD or RxD pin. The initial states are the marking transmit state, and the idle receive state (waiting for a start bit).
214
Initialize Clear TE and RE bits to 0 in SCR Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) (1)
Select transmit/receive format in SMR (2)
Set value to BRR Wait
(3)
1-bit interval elapsed? Yes Set TE or RE to 1 in SCR; Set RIE, TIE, TEIE, and MPIE as necessary
No
(4)
End
Figure 12.3 Sample Flowchart for SCI Initialization Transmitting Serial Data (Asynchronous Mode): Figure 12.4 shows a sample flowchart for transmitting serial data. The procedure is as follows (the steps correspond to the numbers in the flowchart): 1. SCI status check and transmit data write: Read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. 2. To continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in TDR, then clear TDRE to 0.
215
Start transmitting
Read TDRE bit in SSR
(1) No
TDRE = 1? Yes Write transmission data to TDR and clear TDRE bit in SSR to 0 (2) All data transmitted? Yes Read TEND bit in SSR
No
TEND = 1? Yes End transmission
No
Figure 12.4 Sample Flowchart for Transmitting Serial Data In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in the SSR. When TDRE is cleared to 0, the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from the TDR into the transmit shift register (TSR). 2. After loading the data from the TDR into the TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) is set to 1 in the SCR, the SCI requests a transmit-data-empty interrupt (TxI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: a. Start bit: one 0 bit is output. b. Transmit data: seven or eight bits of data are output, LSB first. c. Parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected.
216
d. Stop bit: one or two 1 bits (stop bits) are output. e. Marking: output of 1 bits continues until the start bit of the next transmit data. 3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads new data from the TDR into the TSR, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit to 1 in the SSR, outputs the stop bit, then continues output of 1 bits (marking). If the transmit-end interrupt enable bit (TEIE) in the SCR is set to 1, a transmit-end interrupt (TEI) is requested. Figure 12.5 shows an example of SCI transmit operation.
Start bit 0 D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 D0 Parity Stop bit bit D7 0/1 1
1 Serial data
Data
Data D1
1 Idle (marking state)
TDRE
TEND
TxI TxI interrupt interrupt handler writes request data in TDR and clears TDRE to 0 1 frame
TxI interrupt request
TEI interrupt request
Figure 12.5 SCI Transmit Operation in Asynchronous Mode (8-Bit Data with Parity and One Stop Bit) Receiving Serial Data: Figures 12.6 show a sample flowchart for receiving serial data. The procedure is as follows (the steps correspond to the numbers in the flowchart). 1. Receive error handling and break detection: If a receive error occurs, read the ORER, PER, and FER bits of the SSR to identify the error. After executing the necessary error handling, clear ORER, PER, and FER all to 0. Receiving cannot resume if ORER, PER or FER remain set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. 2. SCI status check and receive-data read: Read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. The RxI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 3. Continue receiving serial data: Read the RDR and RDRF bit and clear RDRF to 0 before the stop bit of the current frame is received.
217
Initialization
Start reception
Read ORER, PER, and FER bits in SSR
PER, FER, ORER = 1? No Read the RDRF bit in SSR
Yes (1) Error handling (2)
No
RDRF = 1? Yes Read reception data of RDR and clear RDRF bit in SSR to 0 (3)
No
All data received? Yes Clear the RE bit of SCR to 0
End reception
Figure 12.6 Sample Flowchart for Receiving Serial Data
218
Start of error handling
No
ORER = 1? Yes Overrun error handling
No
FER = 1? Yes Break? No Framing error handling Clear RE bit in SCR to 0 Yes
No
PER = 1? Yes Parity error handling
Clear ORER, PER, and FER to 0 in SSR End
Figure 12.6 Sample Flowchart for Receiving Serial Data (cont)
219
In receiving, the SCI operates as follows: 1. The SCI monitors the communication line. When it detects a start bit (0), the SCI synchronizes internally and starts receiving. 2. Receive data is shifted into the RSR in order from the LSB to the MSB. 3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following checks: a. Parity check. The number of 1s in the receive data must match the even or odd parity setting of the O/E bit in the SMR. b. Stop bit check. The stop bit value must be 1. If there are two stop bits, only the first stop bit is checked. c. Status check. RDRF must be 0 so that receive data can be loaded from the RSR into the RDR. If the data passes these checks, the SCI sets RDRF to 1 and stores the received data in the RDR. If one of the checks fails (receive error), the SCI operates as indicated in table 12.16. Note: When a receive error occurs, further receiving is disabled. While receiving, the RDRF bit is not set to 1, so be sure to clear the error flags. 4. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the SCR, the SCI requests a receive-data-full interrupt (RxI). If one of the error flags (ORER, PER, or FER) is set to 1 and the receive-data-full interrupt enable bit (RIE) in the SCR is also set to 1, the SCI requests a receive-error interrupt (ERI). Figure 12.7 shows an example of SCI receive operation in the asynchronous mode. Table 12.7 Receive Error Conditions and SCI Operation
Receive Error Overrun error Framing error Parity error Abbreviation ORER FER PER Condition Receiving of next data ends while RDRF is still set to 1 in SSR Stop bit is 0 Parity of receive data differs from even/odd parity setting in SMR Data Transfer Receive data not loaded from RSR into RDR Receive data loaded from RSR into RDR Receive data loaded from RSR into RDR
220
1 Serial data
Start bit 0 D0 D1
Data D7
Parity Stop Start bit bit bit 0/1 1 0 D0
Data D1
Parity Stop bit bit D7 0/1 0
1 Idle (marking state)
TDRF RxI interrupt request
FER
1 frame
RxI interrupt handler reads data in RDR and clears RDRF to 0.
Framing error generates ERI interrupt request.
Figure 12.7 SCI Receive Operation (8-Bit Data with Parity and One Stop Bit) 12.3.3 Multiprocessor Communication
The multiprocessor communication function enables several processors to share a single serial communication line for sending and receiving data. The processors communicate in the asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). In multiprocessor communication, each receiving processor is addressed by a unique ID. A serial communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending cycles. The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. Receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their IDs. The receiving processor with a matching ID continues to receive further incoming data. Processors with IDs not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and receive data in this way. Figure 12.8 shows the example of communication among processors using the multiprocessor format.
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Communication Formats: Four formats are available. Parity-bit settings are ignored when the multiprocessor format is selected. For details see table 12.5. Clock: See the description in the asynchronous mode section.
Transmitting processor Serial communication line
Receiving processor A (ID = 01)
Receiving processor B (ID = 02)
Receiving processor C (ID = 03)
Receiving processor D (ID = 04)
Serial data
H'01 (MPB = 1) ID-transmit cycle: receiving processor address
H'AA (MPB = 0) Data-transmit cycle: data sent to receiving processor specified by ID
MPB: Multiprocessor bit
Figure 12.8 Communication Among Processors Using Multiprocessor Format (Sending Data H'AA to Receiving Processor A) Transmitting Multiprocessor Serial Data: Figure 12.9 shows a sample flowchart for transmitting multiprocessor serial data. The procedure is as follows (the steps correspond to the numbers in the flowchart): 1. SCI status check and transmit data write: Read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR). Also set MPBT (multiprocessor bit transfer) to 0 or 1 in SSR. Finally, clear TDRE to 0. 2. Continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in TDR, then clear TDRE to 0.
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Start transmission Read TDRE bit in SSR (1) No
TDRE = 1? Yes Write transmit data in TDR and set MPBT in SSR Clear TDRE bit to 0
All data transmitted? Yes Read TEND bit in SSR
No
(2)
TEND = 1? Yes End transmission
No
Figure 12.9 Sample Flowchart for Transmitting Multiprocessor Serial Data In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in the SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from the TDR into the transmit shift register (TSR). 2. After loading the data from the TDR into the TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCR is set to 1, the SCI requests a transmit-data-empty interrupt (TxI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: a. Start bit: one 0 bit is output. b. Transmit data: seven or eight bits are output, LSB first. c. Multiprocessor bit: one multiprocessor bit (MPBT value) is output. d. Stop bit: one or two 1 bits (stop bits) are output. e. Marking: output of 1 bits continues until the start bit of the next transmit data.
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3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads data from the TDR into the TSR, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in the SSR to 1, outputs the stop bit, then continues output of 1 bits in the marking state. If the transmit-end interrupt enable bit (TEIE) in the SCR is set to 1, a transmit-end interrupt (TEI) is requested at this time. Figure 12.10 shows an example of SCI receive operation in the multiprocessor format.
Multiprocessor bit Stop Start Data bit bit D0 D1 D7 0/1 1 0 D0 Multiprocessor bit Stop Data bit D1 D7 0/1 1
1 Serial data
Start bit 0
1 Idle (marking state)
TDRE
TEND
TxI interrupt request
TxI interrupt handler writes data in TDR and clears TDRE to 0 1 frame
TxI interrupt request
TEI interrupt request
Figure 12.10 SCI Multiprocessor Transmit Operation (8-Bit Data with Multiprocessor Bit and One Stop Bit) Receiving Multiprocessor Serial Data: Figure 12.11 shows a sample flowchart for receiving multiprocessor serial data. The procedure for receiving multiprocessor serial data is listed below. 1. ID receive cycle: Set the MPIE bit in the serial control register (SCR) to 1. 2. SCI status check and compare to ID reception: Read the serial status register (SSR), check that RDRF is set to 1, then read data from the receive data register (RDR) and compare with the processor's own ID. If the ID does not match the receive data, set MPIE to 1 again and clear RDRF to 0. If the ID matches the receive data, clear RDRF to 0. 3. Receive error handling and break detection: If a receive error occurs, read the ORER and FER bits in SSR to identify the error. After executing the necessary error processing, clear both ORER and FER to 0. Receiving cannot resume if ORER or FER remain set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. 4. SCI status check and data receiving: Read SSR, check that RDRF is set to 1, then read data from the receive data register (RDR).
224
Initialization Start reception Set MPIE bit in SCR to 1 Read ORER and FER bits of SSR FER = 1? or ORER =1? No Read RDRF bit in SSR No (2) Yes (1)
RDRF = 1? Yes Read receive data from RDR
No
Is ID the station's ID Yes Read ORER and FER bits in SSR FER = 1? or ORER =1? No Read RDRF bit of SSR RDRF = 1? Yes Read receive data from RDR (3) (4) No Yes
No
All data received? Yes Clear RE bit in SCR to 0 End reception
Error processing
Figure 12.11 Sample Flowchart for Receiving Multiprocessor Serial Data
225
Start error handling
No
ORER = 1? Yes Overrun error handling
No
FER = 1? Yes Break? No Framing error handling Clear RE bit in SCR to 0 Yes
Clear ORER and FER bits in SSR to 0
End
Figure 12.11 Sample Flowchart for Receiving Multiprocessor Serial Data (cont)
226
Figures 12.12 show examples of SCI receive operation using a multiprocessor format.
Start bit 0 Data (ID1) D0 D1 D7 Stop Start Data MPB bit bit (data 1) 1 1 0 D0 D1 D7 Stop MPB bit 0 1
1 Serial data
1
Idling (marking)
MPB
MPIE
RDRF
RDR value RxI interrupt request (multiprocessor interrupt), MPIE = 0 RxI interrupt handler reads data in RDR and clears RDRF to 0
ID1
Not station's ID, so MPIE is set to 1 again
No RxI interrupt, RDR maintains state
(a) ID Does Not Match Start bit 0 Data (ID2) D0 D1 D7 Stop Start Data MPB bit bit (data 2) 1 1 0 D0 D1 D7 Stop MPB bit 0 1
1 Serial data
1
Idling (marking)
MPB
MPIE
RDRF
RDR value
ID1
ID2
Data2
RxI interrupt request (multiprocessor interrupt), MPIE = 0
RxI interrupt handler reads data in RDR and clears RDRF to 0
Station's ID, so receiving MPIE continues, with data bit is again received by the RxI set to 1 interrupt processing routine
(b) ID Matches
Figure 12.12 SCI Receive Operation (8-Bit Data with Multiprocessor Bit and One Stop Bit)
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12.4
Interrupt
The SCI has four interrupt sources: transmit-end (TEI), receive-error (ERI), receive-data-full (RxI), and transmit-data-empty (TxI). Table 12.8 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in the serial control register (SCR). Each interrupt request is sent separately to the interrupt controller. TxI is requested when the TDRE bit in the serial status register (SSR) is set to 1. TDRE is automatically cleared to 0 when a write to the transmit data register (TDR) is performed. RxI is requested when the RDRF bit in the SSR is set to 1. ERI is requested when the ORER, FER, or PER bit in the SSR is set to 1. TEI is requested when the TEND bit in the SSR is set to 1. Where the TxI interrupt indicates that transmit data writing is enabled, the TEI interrupt indicates that the transmit operation has ended. Table 12.8 SCI Interrupt Sources
Interrupt Source ERI RxI TxI TEI Description Receive error (ORER, PER, or FER) Receive data full (RDRF) Transmit data empty (TDRE) Transmit end (TEND) Low Priority High
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12.5
Notes on Use
The following points should be noted when using the SCI. TDR Write and TDRE Flags: The TDRE bit in the serial status register (SSR) is a status flag indicating loading of transmit data from TDR into TSR. The SCI sets TDRE to 1 when it transfers data from TDR to TSR. Data can be written to TDR regardless of the TDRE bit status. If new data is written in TDR when TDRE is 0, however, the old data stored in TDR will be lost because the data has not yet been transferred to the TSR. Before writing transmit data to the TDR, be sure to check that TDRE is set to 1. Simultaneous Multiple Receive Errors: Table 12.9 indicates the state of the SSR status flags when multiple receive errors occur simultaneously. When an overrun error occurs, the RSR contents cannot be transferred to the RDR, so receive data is lost. Table 12.9 SSR Status Flags and Transfer of Receive Data
SSR Status Flags Receive Error Status Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error RDRF 1 0 0 1 1 0 1 ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Transfer RSR RDR X O O X X O X
Note: O = Receive data is transferred from RSR to RDR. X = Receive data is not transferred from RSR to RDR.
Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state, the input from the RxD pin consists of all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state, the SCI receiver continues to operate, so if the FER bit is cleared to 0, it will be set to 1 again. Receive Data Sampling Timing and Receive Margin: The SCI operates on a base clock of 16 times the bit rate frequency. In receiving, the SCI synchronizes internally with the falling edge of the start bit, which it samples on the base clock. Receive data is latched on the rising edge of the eighth base clock pulse (figure 12.13).
229
16 clocks 8 clocks 0 Base clock -7.5 clocks Receive data (RxD) Synchronization sampling timing Data sampling timing Start bit +7.5 clocks D0 D1 78 15 0 78 15 0 5
Figure 12.13 Receive Data Sampling Timing The receive margin in the asynchronous mode can therefore be expressed as:
M = (0.5 - 1 2N ) - (L - 0.5) F - D - 0.5 N (1 + F) x 100%
M : Receive margin (%) N : Ratio of clock frequency to bit rate (N = 16) D : Clock duty cycle (D = 0-1.0) L : Frame length (L = 9-12) F : Absolute deviation of clock frequency
From the equation above, if F = 0 and D = 0.5 the receive margin is 46.875%:
D = 0.5, F = 0 M = (0.5 - 1/(2 x 16)) x 100% = 46.875%
This is a theoretical value. A reasonable margin to allow in system designs is 20-30%.
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Section 13 A/D Converter (A/D)
13.1 Overview
The A/D converter has 10-bit resolution, and can select from a maximum of seven channels of analog inputs. 13.1.1 Features
The A/D converter has the following features: * 10-bit resolution * Seven input channels * High-speed conversion Minimum conversion time: 6.7 s per channel (for 20-MHz operation) * Two operating modes: single mode or scan mode Single mode: A/D conversion on one channel Scan mode: Continuous A/D conversion on one to four channels * Four 16-bit data registers Conversion results transferred to and stored in data registers corresponding to each channel. * Sample and hold function * A/D conversion end interrupt generation An A/D conversion end interrupt (ADI) request can be generated on completion of A/D conversion. * A/D conversion can be started by MTU trigger input.
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13.1.2
Block Diagram
Figure 13.1 is the block diagram of the A/D converter.
Module data bus
ADDRA
ADDRC
ADDRB
ADDRD
ADCSR
AVcc AVss 10-bit D/A
Successive approximations register
AN0 AN1 AN2 AN3 AN4 AN5 AN6
+
Analog multiplexer
- Comparator Control circuit Sample and hold circuit
ADCR
Bus interface
Internal data bus
/8
/16
ADI interrupt signal A/D converter ADCR: ADDCSR: ADDRA: ADDRB: ADDRC: ADDRD: A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D MTU trigger
Figure 13.1 A/D Converter Block Diagram
232
13.1.3
Pin Configuration
Table 13.1 shows the input pins used by the A/D converter. The seven analog input pins are divided into two groups: group 0, comprising analog input pins 0- 3 (AN0-AN3), and group 1, comprising analog input pins 4-6 (AN4-AN6). The AVCC and AVSS pins are for the A/D converter internal analog section power supply. Table 13.1 Pin Configuration
Pin Analog supply Analog ground Analog input 0 Analog input 1 Analog input 2 Analog input 3 Analog input 4 Analog input 5 Analog input 6 Abbreviation AVCC AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 I/O I I I I I I I I I Analog input group 1 Function Analog section power supply Analog section ground and A/D conversion reference voltage Analog input group 0
233
13.1.4
Register Configuration
Table 13.2 shows the configuration of the A/D converter registers. Table 13.2 Register Configuration
Name A/D data register AH A/D data register AL A/D data register BH A/D data register BL A/D data register CH A/D data register CL A/D data register DH A/D data register DL Abbreviation R/W ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL R R R R R R R R Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 Address H'FFFF8420 H'FFFF8421 H'FFFF8422 H'FFFF8423 H'FFFF8424 H'FFFF8425 H'FFFF8426 H'FFFF8427 H'FFFF8428 H'FFFF8429 Access Size 8,16 16 8,16 16 8,16 16 8,16 16 8,16 8,16
A/D control/status register ADCSR A/D control register ADCR
R/(W)* H'00 R/W H'7F
Note: Only 0 can be written to bit 7 to clear the flag.
13.2
13.2.1
Register Descriptions
A/D Data Registers A-D (ADDRA-ADDRD)
The A/D data registers (ADDR) are 16-bit read-only registers for storing A/D conversion results. There are four of these registers, ADDRA through ADDRD. The A/D-converted data is 10-bit data which is transferred to the ADDR for the selected channel for storage. The upper 8 bits of the converted data correspond to the upper byte of the ADDR, and the lower 2 bits correspond to the lower byte. Bits 5-0 of the lower byte of the ADDR are reserved, and always read 0. Table 13.3 shows the correspondence between the analog input channels and the ADDR registers. The ADDR registers can be read by the CPU at all times. The upper byte is read directly, but the lower byte data is transferred via a temporary register (TEMP). For details, see section 13.3, CPU Interface. The ADDR registers are initialized to H'0000 by a power-on reset.
234
Bit: ADDRn: Initial value: R/W: Bit: ADDRn: Initial value: R/W: (n = A-D)
15 AD9 0 R 7 AD1 0 R
14 AD8 0 R 6 AD0 0 R
13 AD7 0 R 5 -- 0 R
12 AD6 0 R 4 -- 0 R
11 AD5 0 R 3 -- 0 R
10 AD4 0 R 2 -- 0 R
9 AD3 0 R 1 -- 0 R
8 AD2 0 R 0 -- 0 R
Table 13.3 Correspondence between Analog Input Channels and ADDRA-ADDRD
Analog Input Channel Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 -- A/D Data Register ADDRA ADDRB ADDRC ADDRD
13.2.2
A/D Control/Status Register (ADCSR)
The ADCSR is an 8-bit read/write register used for A/D conversion operation control and to indicate status. The ADCSR is initialized to H'00 by power-on reset.
Bit: 7 ADF Initial value: R/W: 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W
Note: The only value that can be written is a 0 to clear the flag.
235
* Bit 7--A/D End Flag (ADF): This status flag indicates that A/D conversion has ended.
Bit 7: ADF 0 Description Clear conditions (initial value) With ADF = 1, by reading the ADF flag then writing 0 in ADF 1 Set conditions * * Single mode: When A/D conversion ends after conversion for all designated channels Scan mode: After one round of A/D conversion for all specified channels
* Bit 6--A/D Interrupt Enable (ADIE): Enables or disables interrupt requests (ADI) after A/D conversion ends.
Bit 6: ADIE 0 1 Description Disables interrupt requests (ADI) after A/D conversion ends (initial value) Enables interrupt requests (ADI) after A/D conversion ends
* Bit 5--A/D Start (ADST): Selects start or stop for A/D conversion. The ADST bit remains set to 1 during A/D conversion. It can also be set to 1 by MTU trigger input.
Bit 5: ADST 0 1 Description A/D conversion halted (initial value) Single mode: Start A/D conversion. Automatically cleared to 0 after conversion for the designated channel ends. Scan mode: Start A/D conversion. Continuous conversion until 0 cleared by software, and by power-on reset.
* Bit 4--Scan Mode (SCAN): Selects single mode or scan mode for A/D conversion. For details of the operation in single mode and scan mode, see section 13.4, Operation. Change the mode only when ADST = 0.
Bit 4: SCAN 0 1 Description Single mode (initial value) Scan mode
236
* Bit 3--Clock Select (CKS): Sets the A/D conversion time. Change the conversion time only when ADST = 0.
Bit 3: CKS 0 1 Description Conversion time = 266 states (max.) (initial value) Conversion time = 134 states (max.)
* Bits 2-0--Channel Select 2-0 (CH2-CH0): These bits, along with the SCAN bit, select the analog input channel. Change the channel selection only when ADST = 0.
Description Bit 2: CH2 0 0 0 0 1 1 1 1 Note: Bit 1: CH1 0 0 1 1 0 0 1 1 Bit 0: CH0 0 1 0 1 0 1 0 1 Single Mode AN0 (initial value) AN1 AN2 AN3 AN4 AN5 AN6 Reserved* Scan Mode AN0 (initial value) AN0-AN1 AN0-AN2 AN0-AN3 AN4 AN4, AN5 AN4-AN6 Reserved*
This setting is reserved and must not be used.
13.2.3
A/D Control Register (ADCR)
The A/D control register (ADCR) is an 8-bit read/write register that enables or disables starting of A/D conversion by MTU trigger input. The ADCR is initialized to H'7F by a power-on reset or in standby mode.
Bit: 7 TRGE Initial value: R/W: 0 R/W 6 -- 1 R 5 -- 1 R 4 -- 1 R 3 -- 1 R 2 -- 1 R 1 -- 1 R 0 -- 1 R
237
* Bit 7--Trigger Enable (TRGE): Enables or disables starting of A/D conversion by MTU trigger input.
Bit 7: TRGE 0 1 Description Disables A/D conversion start by MTU trigger input (initial value) A/D conversion is started by MTU trigger
* Bits 6-0--Reserved: These bits always read 1. The write value should always be 1.
13.3
CPU Interface
ADDRA-ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus. Therefore, while the upper byte is accessed directly by the CPU, the lower byte is accessed via an 8-bit temporary register (TEMP). Data is read from an ADDR register as follows. When the upper byte is read, the upper-byte value is transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading an ADDR register, always read the upper byte before the lower byte. This operation can be performed by reading ADDR from the upper byte address using a word transfer instruction (such as MOV.W). It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 13.2 shows the data flow for access to an ADDR register.
238
Upper-byte read Module data bus
CPU (H'AA)
Bus interface
TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A-D) Lower-byte read Module data bus
CPU (H'40)
Bus interface
TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A-D)
Figure 13.2 ADDR Access Operation (Reading H'AA40)
239
13.4
Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode.. The operation in these two modes is described below. 13.4.1 Single Mode (SCAN = 0)
Single mode should be selected for A/D conversion on only one channel. A/D conversion starts when the ADST bit in the A/D control/status register (ADCSR) is set to 1 by software or MTU trigger input. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. When conversion ends, the ADF bit in ADCSR is set to 1. If the ADIE bit in ADCSR is also 1, an ADI interrupt is requested. To clear the ADF bit, first read ADF when set to 1, then write 0 in ADF. To prevent incorrect operation, A/D conversion should be halted by clearing the ADST bit to 0 before changing the mode or analog input channel. After the change is made, A/D conversion is restarted by setting the ADST bit to 1 (the mode or channel change and setting of the ADST bit can be carried out simultaneously). An example of the operation when analog input channel 1 (AN1) is selected and A/D conversion is performed in single mode is described below. Figure 13.3 shows a timing diagram for this example. 1. Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = CH1 = 0, CH0 = 1), the A/D interrupt request is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). 2. When A/D conversion is completed, the result is transferred to ADDRB. At the same time ADF is set to 1, ADST is cleared to 0, and the A/D converter becomes idle. 3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. 4. The A/D interrupt service routine is started. 5. The routine reads ADF set to 1, then writes 0 in ADF. 6. The routine reads and processes the conversion result (ADDRB). 7. Execution of the A/D interrupt service routine ends. After this, if the ADST bit is set to 1, A/D conversion starts again and steps 2 to 7 are repeated.
240
Set*
ADIE Set* A/D conversion starts Clear* Clear* Set*
ADST
ADF Conversion standby
Channel 0 (AN0) Conversion standby A/D conversion 1 Conversion standby
Channel 1 (AN1) Conversion standby
A/D conversion 2
Conversion standby
Channel 2 (AN2) Conversion standby
Channel 3 (AN3)
ADDRA Conversion result read A/D conversion result 1 Conversion result read A/D conversion result 2
ADDRB
ADDRC
ADDRD
Figure 13.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
Note: Vertical arrows ( ) indicate instructions executed by software.
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13.4.2
Scan Mode (SCAN = 1)
Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit in the A/D control/status register (ADCSR) is set to 1 by software or MTU trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0; AN4 when CH1 = 1). When more than one channel has been selected, A/D conversion starts on the second channel (AN1 or AN5) as soon as conversion ends on the first channel. A/D conversion is performed repeatedly on all the selected channels until the ADST bit is cleared to 0. The conversion results are transferred to and stored in the ADDR register for each channel. To prevent incorrect operation, A/D conversion should be halted by clearing the ADST bit to 0 before changing the mode or analog input channels. After the change is made, the first channel is selected and A/D conversion is restarted by setting the ADST bit to 1 (the mode or channel change and setting of the ADST bit can be carried out simultaneously). An example of the A/D conversion operation in scan mode when three channels (AN0-AN2) in group 0 are selected is described below. Figure 13.4 shows a timing diagram for this example. 1. Scan mode is selected (SCAN = 1), group 0 is selected as the scan group (CH2 = 0), analog input channels AN0-AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). 2. A/D conversion starts on the first channel (AN0), and when completed, the result is transferred to ADDRA. Next, conversion of the second channel (AN1) starts automatically. 3. Conversion proceeds in the same way through the third channel (AN2). 4. When conversion is completed for all the selected channels (AN0-AN2), ADF is set to 1, the first channel (AN0) is selected again, and conversion is performed on that channel. If the ADIE bit is also 1, an ADI interrupt is requested when conversion is completed. 5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After this, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0).
242
Continuous A/D conversion Set Clear*1 Clear*1
*1
ADST
ADF
hannel 0 (AN0)
Conversion standby
A/D conversion 1
Conversion standby
A/D conversion 4
Conversion standby
hannel 1 (AN1) Conversion standby
A/D conversion 2
Conversion standby
A/D conversion 5
*2
Conversion standby
hannel 2 (AN2) Conversion standby
A/D conversion 3
hannel 3 (AN3) Transfer A/D conversion result 1
Conversion standby
ADDRA
A/D conversion result 4
ADDRB
A/D conversion result 2
ADDRC
A/D conversion result 3
ADDRD
Figure 13.4 Example of A/D Converter Operation (Scan Mode, Channels AN0-AN2 Selected)
Notes: 1. Vertical arrows ( ) indicate instructions executed by software. 2. Data currently being converted is ignored.
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13.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample and hold circuit. The A/D converter samples the analog input at time tD after the ADST bit is set to 1 in the A/D control/status register (ADCSR), then starts conversion. Figure 13.5 shows the A/D conversion timing, and table 13.4 shows A/D conversion times. As shown in figure 13.5, A/D conversion time tCONV consists of A/D conversion start delay time tD and analog input sampling time tSPL. The length of tD is not fixed, but is determined by the timing of the write to ADSCR. The total conversion time therefore varies within the ranges shown in table 13.4. In scan mode, the tCONV values given in table 13.4 apply to the first conversion. In the second and subsequent conversions, tCONV is fixed at 256 states when CKS = 0 or 128 states when CKS = 1.
244
(1) CK
Address
(2)
Write signal
Input sampling timing
ADF tD tSPL tCONV (1): (2): tD: tSPL: tCONV: ADCSR write cycle ADCSR address A/D conversion start delay time Input sampling time A/D conversion time
Figure 13.5 A/D Conversion Timing Table 13.4 A/D Conversion Times (Single Mode)
CKS = 0 Symbol A/D conversion start delay time Input sampling time A/D conversion time Note: Unit: states (tcyc ) tD t SPL t CCNV Min 10 -- 259 Typ -- 64 -- Max 17 -- 266 Min 6 -- 131 CKS = 1 Typ -- 32 -- Max 9 -- 134
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13.4.4
MTU Trigger Input Timing
A/D conversion can also be started by MTU trigger input. When the TRGE bit is set to 1 in the A/D control register (ADCR), input from the MTU functions as trigger input. When an MTU trigger is detected, the ADST bit is set to 1 in the A/D control/status register (ADST), and the A/D converter is started. Other operations, for both single mode and scan mode, are the same as when the ADST bit is set to 1 by software, . Figure 13.6 shows the timing for MTU trigger input.
CK
MTU trigger signal
ADST A/D conversion
Figure 13.6 External Trigger Input Timing
13.5
A/D Conversion Precision Definitions
The A/D converter converts analog values input from analog input channels to 10-bit digital values by comparing them with an analog reference voltage. In this operation, the absolute precision of the A/D conversion (i.e. the deviation between the input analog value and the output digital value) includes the following kinds of error. 1. 2. 3. 4. Offset error Full-scale error Quantization error Nonlinearity error
246
The above four kinds of error are described below with reference to figure 13.7. For the sake of clarity, this figure shows 3-bit A/D conversion rather than 10-bit A/D conversion. Offset error (see figure 13.7 (1)) is the deviation between the actual A/D conversion characteristic and the ideal A/D conversion characteristic when the digital output value changes from the minimum value (zero voltage) of 0000000000 (000 in the figure) to 0000000001 (001 in the figure ). Full-scale error (see figure 13.7 (2)) is the deviation between the actual A/D conversion characteristic and the ideal A/D conversion characteristic when the digital output value changes from 1111111110 (110 in the figure) to the maximum value (full-scale voltage) of 111111111 (111 in the figure). Quantization error is the deviation inherent in the A/D converter, given by 1/2 LSB (see figure 13.7 (3)). Nonlinearity error is the deviation between the actual A/D conversion characteristic and the ideal A/D conversion characteristic from zero voltage to full-scale voltage (see figure 13.7 (4)). This does not include offset error, full-scale error, and quantization error.
(2) Full-scale error
Digital output
Digital output
111 110 101 100 011 010 001 000 0
Ideal A/D conversion characteristic
Ideal A/D conversion characteristic
(4) Nonlinearity error (3) Quantization error Actual A/D conversion characteristic
1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS FS
Analog input voltage FS: Full-scale voltage
(1) Offset error
Analog input voltage
Figure 13.7
A/D Conversion Precision Definitions
247
13.6
Notes on Use
The following points should be noted when using the A/D converter. 13.6.1 Analog Voltage Settings
Analog Input Voltage Range: The voltage applied to analog input pins during A/D conversion should be in the range AVSS ANn AV CC (n = 0 to 6). AVCC and AV SS input voltages: For the AV CC and AVSS input voltages, set AVCC = 3.3 V 10%, and AVSS = VSS . When the A/D converter is not used, set AVCC = VCC and AVSS = VSS . 13.6.2 Handling of Analog Input Pins
To prevent damage from surges and other abnormal voltages at the analog input pins (AN0-AN6), connect a protection circuit such as that shown in figure 13.8. This circuit also includes a CR filter function that suppresses error due to noise. The circuit shown here is only a design example; circuit constants must be decided on the basis of the actual operating conditions. Figure 13.9 shows an equivalent circuit for the analog input pins, and table 13.5 summarizes the analog input pin specifications.
AVcc 100 AN0-AN6 * 0.1 F AVss SH7011
Note:
10 F
0.01 F
Figure 13.8 Example of Analog Input Pin Protection Circuit
248
1.0 k AN0-AN6
20 pF
1 M
Analog multiplexer Note: Values are reference values.
A/D converter
Figure 13.9 Analog Input Pin Equivalent Circuit Table 13.5 Analog Input Pin Specifications
Item Analog input capacitance Permitted signal source impedance Min -- -- Max 20 3 Unit pF k
249
Section 14 Pin Function Controller
14.1 Overview
The pin function controller (PFC) is composed of registers for selecting the function of multiplexed pins and the direction of input/output. Table 14.1 lists the SH7011's multiplexed pins. These multiplexed pins are initially set as input ports after a power-on reset. Table 14.1 Multiplexed Pins
Port E E E E E E Function 1 (Related Module) PE7 I/O (port) PE6 I/O (port) PE5 I/O (port) PE4 I/O (port) PE2 I/O (port) PE0 I/O (port) Function 2 (Related Module) TIOC2B I/O (MTU) TIOC2A I/O (MTU) TIOC1B I/O (MTU) TIOC1A I/O (MTU) TIOC0C I/O (MTU) TIOC0A I/O (MTU) Pin 98 83 82 81 79 78
14.2
Register Configuration
Table 14.2 summarizes the registers of the pin function controller. Table 14.2 Register Configuration
Name Port A I/O register H Port E I/O register Abbreviation R/W PAIORH PEIOR R/W R/W R/W Initial Value H'0000 H'0000 H'0000 Address H'FFFF8384 H'FFFF8385 H'FFFF83B4 H'FFFF83B5 H'FFFF83BA H'FFFF83BB Access Size 8, 16 8, 16 8, 16
Port E control register 2 PECR2
251
14.3
14.3.1
Register Descriptions
Port A I/O Register H (PAIORH)
Port A I/O register H (PAIORH) is a 16-bit read/write register that selects input or output for pins PA19 and PA18 in port A. A pin in port A is an output pin if its corresponding PAIORH bit is set to 1, and an input pin if the bit is cleared to 0. PAIORH is initialized to H'0000 by a power-on reset; however, it is not initialized in sleep mode, so the previous data is maintained.
Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 PA19 IOR 0 R/W 10 -- 0 R 2 PA18 IOR 0 R/W 9 -- 0 R 1 -- 0 R 8 -- 0 R 0 -- 0 R
14.3.2
Port E I/O Register (PEIOR)
The port E I/O register (PEIOR) is a 16-bit read/write register that selects input or output for nine pins in port E. Bits PE17IOR-PE4IOR, PE2IOR, and PE0IOR correspond to multiplexed pins. When the port E pin functions are PEX, a pin in port E is an output pin if its corresponding PEIOR bit is set to 1, and an input pin if the bit is cleared to 0. PEIOR is initialized to H'0000 by a power-on reset; however, it is not initialized in sleep mode, so the previous data is maintained.
Bit: 15 -- Initial value: R/W: 0 R 14 PE14 IOR 0 R/W 13 PE13 IOR 0 R/W 12 PE12 IOR 0 R/W 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R
252
Bit:
7 PE7 IOR
6 PE6 IOR 0 R/W
5 PE5 IOR 0 R/W
4 PE4 IOR 0 R/W
3 -- 0 R
2 PE2 IOR 0 R/W
1 -- 0 R
0 PE0 IOR 0 R/W
Initial value: R/W:
0 R/W
14.3.3
Port E Control Register 2 (PECR2)
Port E control register 2 (PECR2) is a 16-bit read/write register that selects the functions of the six multiplexed pins in port E. PECR2 is initialized to H'0000 by a power-on reset; however, it is not initialized in sleep mode, so the previous data is maintained.
Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 PE7MD 0 R/W 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 PE6MD 0 R/W 4 PE2 MD0 0 R/W 11 -- 0 R 3 -- 0 R 10 PE5MD 0 R/W 2 -- 0 R 9 -- 0 R 1 -- 0 R 8 PE4MD 0 R/W 0 PE0 MD0 0 R/W
* Bit 15--Reserved: This bit always reads as 0. The write value should always be 0. * Bit 14--PE7 Mode (PE7MD): Selects the function of the PE7/TIOC2B pin.
Bit 14: PE7MD 0 1 Description General input/output (PE7) (initial value) MTU input capture input/output compare output (TIOC2B)
* Bit 13 --Reserved: This bit always reads as 0. The write value should always be 0.
253
* Bit 12--PE6 Mode (PE6MD): Selects the function of the PE6/TIOC2A pin.
Bit 12: PE6MD 0 1 Description General input/output (PE6) (initial value) MTU input capture input/output compare output (TIOC2A)
* Bit 11--Reserved: This bit always reads as 0. The write value should always be 0. * Bit 10--PE5 Mode (PE5MD): Selects the function of the PE5/TIOC1B pin.
Bit 10: PE5MD 0 1 Description General input/output (PE5) (initial value) MTU input capture input/output compare output (TIOC1B)
* Bit 9--Reserved: This bit always reads as 0. The write value should always be 0. * Bit 8--PE4 Mode (PE4MD): Selects the function of the PE4/TIOC1A pin.
Bit 8: PE4MD 0 1 Description General input/output (PE4) (initial value) MTU input capture input/output compare output (TIOC1A)
* Bits 7-5--Reserved. These bits always read 0. The write value should always be 0. * Bit 4--PE2 Mode 0 (PE2MD0): Selects the function of the PE2/TIOC0C pin.
Bit 4: PE2MD0 0 1 Description General input/output (PE2) (initial value) MTU input capture input/output compare output (TIOC0C)
* Bits 3-1--Reserved. These bits always read 0. The write value should always be 0. * Bit 0--PE0 Mode 0 (PE0MD0): Selects the function of the PE0/TIOC0A pin.
Bit 0: PE0MD0 0 1 Description General input/output (PE0) (initial value) MTU input capture input/output compare output (TIOC0A)
254
Section 15 I/O Ports (I/O)
15.1 Overview
There are two ports, A and E. The pin function controller (PFC) is used to select the function of multiplexed pins. The ports each have one data register for storing pin data. All pins are initially set as input port pins after a power-on reset.
15.2
Port A
Port A is a 2-pin input/output port, as shown in figure 15.1.
Port A
PA19 (input/output) PA18 (input/output)
Figure 15.1 Port A 15.2.1 Register Configuration
Table 15.1 summarizes the port A register. Table 15.1 Port A Register
Name Port A data register H Abbreviation PADRH R/W R/W Initial Value H'0000 Address H'FFFF8380 H'FFFF8381 Access Size 8, 16
255
15.2.2
Port A Data Register H (PADRH)
PADRH is a 16-bit read/write register that stores data for port A. The bits PA19DR-PA18DR correspond to the PA19 pin and PA18 pin. When the pins are used as ordinary outputs, they will output whatever value is written in the PADRH; when PADRH is read, the register value will be output regardless of the pin status. When the pins are used as ordinary inputs, the pin status rather than the register value is read directly when PADRH is read. When a value is written to PADRH, that value can be written into PADRH, but it will not affect the pin status. Table 15.2 shows the read/write operations of the port A data register. PADRH is initialized by an external power-on reset. However, PADRH is not initialized in sleep mode, so the previous data is maintained.
Bit: 15 -- Initial value: R/W: Bit: 0 R 7 -- Initial value: R/W: 0 R 14 -- 0 R 6 -- 0 R 13 -- 0 R 5 -- 0 R 12 -- 0 R 4 -- 0 R 11 -- 0 R 3 10 -- 0 R 2 9 -- 0 R 1 -- 0 R 8 -- 0 R 0 -- 0 R
PA19DR PA18DR 0 R/W 0 R/W
Table 15.2 Port A Data Register (PADR) Read/Write Operations
PAIOR 0 1 Pin Function Input Output Read Pin status PADR value Write Can write to PADR, but it has no effect on pin status Value written is output by pin
256
15.3
Port E
Port E is a 9-pin input/output port, as shown in table 15.2.
PE14 (I/O) PE13 (I/O) PE12 (I/O) PE7 (I/O)/TIOC2B (I/O) Port E PE6 (I/O)/TIOC2A (I/O) PE5 (I/O)/TIOC1B (I/O) PE4 (I/O)/TIOC1A (I/O) PE2 (I/O)/TIOC0C (I/O) PE0 (I/O)/TIOC0A (I/O)
Figure 15.2 Port E 15.3.1 Register Configuration
Table 15.3 summarizes the port E register. Table 15.3 Port E Register
Name Port E data register Abbreviation PEDR R/W R/W Initial Value H'0000 Address H'FFFF83B0 H'FFFF83B1 Access Size 8, 16
257
15.3.2
Port E Data Register (PEDR)
PEDR is a 16-bit read/write register that stores data for port E. Table 15.5 shows the correspondence between PEDR bits and port E pins. When the pins are used as ordinary outputs, they will output whatever value is written in the PEDR; when PEDR is read, the register value will be read regardless of the pin status. When the pins are used as ordinary inputs, the pin status rather than the register value is read directly when PEDR is read. When a value is written to PEDR, that value can be written into PEDR, but it will not affect the pin status. Table 15.4 shows the read/write operations of the port E data register. PEDR is initialized by a power-on reset. However, PEDR is not initialized for a sleep mode, so the previous data is retained.
Bit: 15 -- Initial value: R/W: Bit: 0 R 7 PE7DR Initial value: R/W: 0 R/W 14 13 12 11 -- 0 R 3 -- 0 R 10 -- 0 R 2 PE2DR 0 R/W 9 -- 0 R 1 -- 0 R 8 -- 0 R 0 PE0DR 0 R/W
PE14DR PE13DR PE12DR 0 R/W 6 0 R/W 5 0 R/W 4 PE4DR 0 R/W
PE6DR PE5DR 0 R/W 0 R/W
Table 15.4 Read/Write Operation of the Port E Data Register (PEDR)
PEIOR 0 Pin Status Ordinary input Other function 1 Ordinary output Other function Read Pin status Pin status PEDR value PEDR value Write Can write to PEDR, but it has no effect on pin status Can write to PEDR, but it has no effect on pin status Value written is output by pin Can write to PEDR, but it has no effect on pin status
258
Table 15.5 Correspondence between Port E Data Register (PEDR) Bits and Port E Pins
PEDR Bit PE14DR PE13DR PE12DR PE7DR PE6DR PE5DR PE4DR PE2DR PE0DR Port E Pin PE14 PE13 PE12 PE7/TIOC2B PE6/TIOC2A PE5/TIOC1B PE4/TIOC1A PE2/TIOC0C PE0/TIOC0A
259
Section 16 RAM
16.1 Overview
The SH7011 has 4 kbytes of on-chip RAM. The on-chip RAM is connected to the CPU by a 32-bit data bus (figure 16.1). The CPU can access data in the on-chip RAM in 8, 16, or 32 bit widths. On-chip RAM data can always be accessed in one state, making the RAM ideal for use as a program area, stack area, or data area, which require high-speed access. The contents of the onchip RAM are held in sleep mode. Memory area addresses H'FFFFE000 to H'FFFFFFFF are allocated to the on-chip RAM.
Internal data bus (32 bits)
H'FFFFF000 H'FFFFF004
H'FFFFF001 H'FFFFF005
H'FFFFF002 H'FFFFF006
H'FFFFF003 H'FFFFF007
On-chip RAM
H'FFFFFFFC
H'FFFFFFFD
H'FFFFFFFE
H'FFFFFFFF
Figure 16.1 Block Diagram of RAM
261
Section 17 Electrical Characteristics
17.1 Absolute Maximum Ratings
Table 17.1 Absolute Maximum Ratings
Item Power supply voltage Input voltage (other than A/D ports) Input voltage (A/D ports) Analog supply voltage Analog input voltage Operating temperature Storage temperature Note: Symbol VCC Vin Vin AVCC VAN Topr Tstg Rating -0.3 to +7.0 -0.3 to VCC + 0.3 -0.3 to AVCC + 0.3 -0.3 to +7.0 -0.3 to AVCC + 0.3 -20 to +75 -55 to +125 Unit V V V V V C C
Operating the LSI in excess of the absolute maximum ratings may result in permanent damage.
263
17.2
DC Characteristics
Table 17.2 DC Characteristics (Conditions: VCC = 3.0 to 3.6V, AV CC = 3.0 to 5.5V, AVCC V CC , VSS = AVSS = 0V, T a = 20 to +75C)
Item Pin Symbol Min VIH Typ Max VCC+ 0.3 Measurement Unit Conditions V
Input high- RES, NMI, PE0, PE2, level PE4 to PE7, voltage PE12 to PE14 EXTAL A/D port Other input pins Input lowlevel voltage RES, NMI, PE0, PE2, PE4 to PE7, PE12 to PE14 Other input pins Schmitt PE0, PE2, trigger input PE4 to PE7, voltage PE12 to PE14 Input leak current RES, NMI, PE0, PE2, PE4 to PE7, PE12 to PE14 A/D port Other input pins Three-state A21-A1, leak current D15-D0, (while off) CS3-CS0, WRx, RD, Port A, E
VCC - 0.7 --
VCC x 0.7 -- 2.2 2.2 VIL -0.3 -- -- --
VCC+ 0.3
V
AVCC+ 0.3 V VCC+ 0.3 VCCx 0.1 V V
VT+ VT- VT - VT | lin |
+ -
-0.3 -- VCCx 0.9 -- -- -- VCCx 0.07 -- -- --
VCCx 0.2 -- VCCx 0.2 -- 1.0
V V V V A Vin= 0.5 to VCC- 0.5V
-- -- | ITSI | --
-- -- --
1.0 1.0 1.0
A A A
Vin= 0.5 to AVCC- 0.5V Vin= 0.5 to VCC- 0.5V Vin= 0.5 to VCC- 0.5V
264
Table 17.2 DC Characteristics (Conditions: VCC = 3.0 to 3.6V, AV CC = 3.0 to 5.5V, AVCC V CC , VSS = AVSS = 0V, T a = 20 to +75C) (cont)
Item Output high-level voltage Pin All output pins Symbol Min VOH Typ Max -- -- 0.4 Measurement Unit Conditions V V V I OH = -200 A I OH = -1mA I OL = 1.6mA
VCC- 0.5 -- VCC- 1.0 --
Output low- All output pins level voltage Input capacitance RES NMI All other input pins During normal operations During sleep mode
VOL
--
--
Cin
-- -- --
-- -- -- 80 70 4
80 50 20 130 110 8
pF pF pF
Vin= 0V f = 1 MHz Ta = 25C
Current consumption Analog supply current
I CC
-- --
mA f = 20MHz mA f = 20MHz mA f = 20MHz
AI CC
--
Notes: 1. Do not release AVCC and AVSS pins when not using the A/D converter. Connect AVCC pin to VCC and AVSS pin to VSS . 2. The value for consumed current is with conditions of VIHmin = VCC - 0.5V and VILmax = 0.5V, with no burden on any of the output pins.
265
Table 17.3 Permitted Output Current Values (Conditions: VCC = 3.0 to 3.6V, AV CC = 3.0 to 5.5V, AVCC V CC , VSS = AVSS = 0V, T a = 20 to +75C)
Item Output low-level permissible current (per pin) Output low-level permissible current (total) Output high-level permissible current (per pin) Output high-level permissible current (total) Symbol I OL IOL -I OH (-IOH ) Min -- -- -- -- Typ -- -- -- -- Max 2.0 80 2.0 25 Unit mA mA mA mA
Note: To assure LSI reliability, do not exceed the output values listed in this table.
17.3
17.3.1
AC Characteristics
Clock Timing
CC
Table 17.4 Clock Timing (Conditions: VCC = 3.0 to 3.6V, AV CC = 3.0 to 5.5V, AV CC V VSS = AVSS = 0V, T a = 20 to +75C)
Item Operating frequency Clock cycle time Clock low-level pulse width Clock high-level pulse width Clock rise time Clock fall time EXTAL clock input frequency EXTAL clock input cycle time EXTAL clock low-level input pulse width EXTAL clock high-level input pulse width EXTAL clock input rise time EXTAL clock input fall time Reset oscillation settling time Symbol Min f OP t cyc t CL t CH t CR t CF f EX t EXcyc t EXL t EXH t EXR t EXF t OSC1 4 50 10 10 -- -- 4 50 10 10 -- -- 20 Max 20 250 -- -- 10 10 20 250 -- -- 5 5 -- Unit MHz ns ns ns ns ns MHz ns ns ns ns ns ms 17.3 17.2
,
Figures 17.1
266
tcyc tCH tCL
CK
1/2VCC tCF
1/2VCC tCR
Figure 17.1 System Clock Timing
tEXcyc tEXH tEXL
EXTAL
1/2VCC
VIH
VIH VIL tEXF VIL
VIH 1/2VCC tEXR
Figure 17.2 EXTAL Clock Input Timing
CK
VCC
VCC min
tOSC1
RES
Figure 17.3 Oscillation Settling Time
267
17.3.2
Control Signal Timing
Table 17.5 Control Signal Timing (Conditions: V CC = 3.0 to 3.6V, AV CC = 3.0 to 5.5V, AVCC V CC , VSS = AVSS = 0V, T a = 20 to +75C)
Item RES rise/fall RES pulse width NMI rise/fall RES setup time * NMI setup time (during edge detection) IRQ7-IRQ0 setup time (edge detection) IRQ7-IRQ0 setup time (level detection) NMI hold time IRQ7-IRQ0 hold time Symbol Min t RESr, t RESf -- t RESW 40 Max 200 -- 200 -- -- -- -- -- -- Unit ns t cyc ns ns ns ns ns ns ns 17.5 17.5 17.4 17.5 Figure 17.4
t NMIr, t NMIf -- t RESS t NMIS t IRQES t IRQLS t NMIH t IRQEH 100 100 100 100 50 50
Note: The RES, NMI, and IRQ7-IRQ0 signals are asynchronous inputs, but when the setup times shown here are provided, the signals are considered to have produced changes at clock rise (for RES) or clock fall (for NMI and IRQ7-IRQ0). If the setup times are not provided, recognition is delayed until the next clock rise or fall.
268
CK
tRESf tRESS VIH RES VIL tRESW VIL
tRESr tRESS VIH
Figure 17.4 Reset Input Timing
CK tNMIr,tNMIf tNMIS VIH VIL tIRQEH IRQ edge tIRQES VIH VIL
tNMIH NMI
tIRQLS
IRQ level
Figure 17.5 Interrupt Signal Input Timing
269
17.3.3
Bus Timing
CC
Table 17.6 Bus Timing (Conditions: VCC = 3.0 to 3.6V, AV CC = 3.0 to 5.5V, AV CC V VSS = AVSS = 0V, T a = 20 to +75C)
Item Address delay time CS delay time 1 CS delay time 2 Read strobe delay time 1 Read strobe delay time 2 Read data setup time Read data hold time Write strobe delay time 1 Write strobe delay time 2 Write data delay time Write data hold time WAIT setup time WAIT hold time Read data access time Symbol Min t AD t CSD1 t CSD2 t RSD1 t RSD2 t RDS * t RDH t WSD1 t WSD2 t WDD t WDH t WTS t WTH t ACC * 1 * 5
4
,
Max Unit Figure 40 40 40 40 40 -- -- 40 40 50 -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 17.6, 7 17.8 17.6, 7
3* 3* 3*
3 3
3* 3
3
3* 3 45 0 3* -- 0 20 0 t cyc x (n+2) - 75 t cyc x (n+1.5) - 75 0 5 0
3
3* 3
30* 2 ns
Access time from read strobe t CE* 1 Write address setup time with t AS respect to WR fall Write address hold time with t WR respect to WR fall Write data hold time with respect to WR fall t WRH
Notes: n is the wait number. 1. If the access time is satisfied, then the tRDS need not be satisfied. 2. t WDH (max) is a reference value. 3. The delay time min values are reference values (typ). 4. t RDS is a reference value. 5. Depending on the operating frequency of the chip, there may be no memory that can be connected in no-wait mode. In this case, a wait should be inserted.
270
T1
T2
CK
tAD
A21-A1
tCSD1
tCSD2
CSn
tRSD1 tOE tRSD2
RD (During read)
tACC tRDS tRDH
D15-D0 (During read)
tWSD1 tWSD2 tWR
WR (During write)
tWRH tAS tWDD tWDH
D15-D0 (During write)
Note:
tRDH is specified from fastest negate timing of A21-A0, CSn and RD.
Figure 17.6 Basic Cycle (No Waits)
271
T1
Tw
T2
CK
tAD
A21-A1
tCSD1
tCSD2
CSn
tRSD1 tOE tRSD2
RD (During read)
tACC tRDS tRDH
D15-D0 (During read)
tWSD1 tWSD2 tWR
WRx (During write)
tAS tWDD tWRH tWDH
D15-D0 (During write) Note : tRDH is specified from fastest negate timing of A21-A0, CSn and RD.
Figure 17.7 Basic Cycle (Software Waits)
272
T1
Tw
Tw
Two
T2
CK
A21-A1
CSn
RD (During read)
D15-D0 (During read) WRx (During write)
D15-D0 (During write) tWTS WAIT tWTH tWTS tWTH
Figure 17.8 Basic Cycle (2 Software Waits + Wait due to WAIT Signal)
273
17.3.4
Multifunction Timer Pulse Unit Timing
Table 17.7 Multifunction Timer Pulse Unit Timing (Conditions:VCC = 3.0 to 3.6V, AV CC = 3.0 to 5.5V, AVCC V CC , VSS = AVSS = 0V, T a = 20 to +75C)
Item Output compare output delay time Input capture input setup time Symbol Min t TOCD t TICS -- 100 Max 100 -- Unit ns ns Figure 17.9
CK tTOCD Output compare output tTICS Input capture input
Figure 17.9 MTU I/O Timing
274
17.3.5
I/O Port Timing
CC
Table 17.8 I/O Port Timing (Conditions:VCC = 3.0 to 3.6V, AV CC = 3.0 to 5.5V, AV CC V VSS = AVSS = 0V, T a = 20 to +75C)
Item Port output data delay time Port input hold time Port input setup time Symbol Min t PWD t PRH t PRS -- 100 100 Max 100 -- -- Unit ns ns ns Figure 17.10
,
T1
T2
CK tPRS Port (Read) tPWD tPRH
Port (Write)
Figure 17.10 I/O Port I/O Timing
275
17.3.6
Serial Communication Interface Timing
Table 17.9 Serial Communication Interface Timing (Conditions:VCC = 3.0 to 3.6V, AV CC = 3.0 to 5.5V, AVCC V CC , VSS = AVSS = 0V, T a = 20 to +75C)
Item Transmit data delay time (clock sync) Receive data setup time (clock sync) Receive data hold time (clock sync) Symbol Min t TXD t RXS t RXH -- 100 100 Max 100 -- -- Unit ns ns ns Figure 17.11
tscyc Internal serial clock tTXD TXD (Transmit data) tRXS RXD (Receive data) tRXH
Figure 17.11 SCI I/O Timing (Clock Sync Mode)
276
17.3.7
A/D Converter Timing
Table 17.10 A/D Converter Timing (Conditions:VCC = 3.0 to 3.6V, AV CC = 3.0 to 5.5V, AV CC VCC , VSS = AVSS = 0V, T a = 20 to +75C)
Item A/D conversion start delay time Symbol Min CKS = 0 t D CKS = 1 Input sampling time CKS = 0 t RXS CKS = 1 A/D conversion time CKS = 0 t RXH CKS = 1 10 6 -- -- 259 131 Typ -- -- 64 32 -- -- Max 17 9 -- -- 266 134 Unit t cyc Figure 17.12
(1) O
Address
(2)
Write signal
Input sampling timing
ADF
tD
tSPL tCONV (1) : ADCSR write cycle (2) : ADCSR address tD : A/D conversion start delay time tSPL : Input sampling time tCONV : A/D conversion time
Figure 17.12 Analog Conversion Timing
277
17.3.8
Measurement Conditions for AC Characteristic
* Input reference levels: High level: 2.2 V Low level: 0.8 V * Output reference levels: High level: 2.0 V Low level: 0.8 V
IOL
LSI output pin
DUT output
CL
V Vref
IOH
Note: CL is set with the following pins, including the total capacitance of the measurement equipment etc: 30 pF: 50 pF: 70 pF: IOL, IOH: CK, CS0-CS3 A21-A1, D15-D0, RD, WRx Port output and peripheral module output pins other than the above. See table 17.3, Permitted Output Current Values.
Figure 17.13 Output Added Circuit
278
17.4
A/D Converter Characteristics
Table 17.11 A/D Converter Characteristics (Conditions:VCC = 3.0 to 3.6V, AV CC = 3.0 to 5.5V, AVCC V CC , VSS = AVSS = 0V, T a = 20 to +75C, CKS = 0)
20 MHz Item Resolution Conversion time Analog input capacity Permission signal source impedance Non-linearity error* Offset error* Full scale error* Quantize error* Absolute error Note: * Reference values Min 10 -- -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- Max 10 13.4 20 1 3 3 3 0.5 4 Unit bit s pF k LSB LSB LSB LSB LSB
Table 17.12 A/D Converter Characteristics (Conditions:VCC = 3.0 to 3.6V, AV CC = 3.0 to 5.5V, AVCC V CC , VSS = AVSS = 0V, T a = 20 to +75C, CKS = 1)
20 MHz Item Resolution Conversion time Analog input capacity Permission signal source impedance Non-linearity error* Offset error* Full scale error* Quantize error* Absolute error Note: * Reference values min 10 -- -- -- -- -- -- -- -- typ 10 -- -- -- -- -- -- -- -- max 10 6.7 20 1 5 5 5 0.5 6 Unit bit s pF k LSB LSB LSB LSB LSB
279
Appendix A On-Chip Supporting Module Registers
Table A.1 On-Chip Supporting Module Registers
Bit Names Bit 6 CHR Bit 5 PE Bit 4 O/E Bit 3 STOP Bit 2 MP Bit 1 CKS1 Bit 0 CKS0 Module SCI
Address Register H'FFFFxxxx Abbr. Bit 7 81B0 81B1 81B2 81B3 81B4 81B5 8240 8241 8260 8261 8262 8263 8264 8265 8266 8267 8268 8269 826A 826B 826C 826D 826E 826F TGR0D TGR0C TGR0B TGR0A SMR BRR SCR TDR SSR RDR TSTR TSYR TCR0 TMDR0 TIOR0H TIOR0L TIER0 TSR0 TCNT0 -- -- CCLR2 -- -- -- TTGE -- TDRE TIE --
RIE
TE
RE
MPIE
TEIE
--
--
RDRF
ORER
FER
PER
TEND
MPB
MPBT
-- -- CCLR1 -- -- -- -- --
-- -- CCLR0 BFB -- -- -- --
-- -- CKEG1 BFA -- -- TCIEV TCFV
-- -- CKEG0 MD3 IOA3 IOC3 TGIED TGFD
CST2 SYNC2 TPSC2 MD2 IOA2 IOC2 TGIEC TGFC
CST1 SYNC1 TPSC1 MD1 IOA1 IOC1 TGIEB TGFB
CST0 SYNC0 TPSC0 MD0 IOA0 IOC0 TGIEA TGFA
Common MTU
Ch0
281
Table A.1
On-Chip Supporting Module Registers (cont)
Bit Names Bit 6 CCLR1 -- IOB2 -- -- Bit 5 CCLR0 -- IOB1 -- -- Bit 4 CKEG1 -- IOB0 TCIEV TCFV Bit 3 CKEG0 MD3 IOA3 -- -- Bit 2 TPSC2 MD2 IOA2 -- -- Bit 1 TPSC1 MD1 IOA1 TGIEB TGFB Bit 0 TPSC0 MD0 IOA0 TGIEA TGFA Module Ch1 MTU
Address Register H'FFFFxxxx Abbr. Bit 7 8280 8281 8282 8284 8285 8286 8287 8288 8289 828A 828B 82A0 82A1 82A2 82A4 82A5 82A6 82A7 82A8 82A9 82AA 82AB 8348 8349 834A 834B 834C 834D 834E 834F 8350 8351 8352 8353 IPRF IPRE IPRD IPRC IPRB IPRA (IRQ0) (IRQ2) (IRQ4) (IRQ6) -- -- (MTU0) (MTU1) (MTU2) -- -- -- TGR2B TGR2A TCR2 TMDR2 TIOR2 TIER2 TSR2 TCNT2 -- -- IOB3 TTGE -- TGR1B TGR1A TCR1 TMDR1 TIOR1 TIER1 TSR1 TCNT1 -- -- IOB3 TTGE --
CCLR1 -- IOB2 -- --
CCLR0 -- IOB1 -- --
CKEG1 -- IOB0 TCIEV TCFV
CKEG0 MD3 IOA3 -- --
TPSC2 MD2 IOA2 -- --
TPSC1 MD1 IOA1 TGIEB TGFB
TPSC0 MD0 IOA0 TGIEA TGFA
Ch2
(IRQ0) (IRQ2) (IRQ4) (IRQ6) -- -- (MTU0) (MTU1) (MTU2) -- -- --
(IRQ0) (IRQ2) (IRQ4) (IRQ6) -- -- (MTU0) (MTU1) (MTU2) -- -- --
(IRQ0) (IRQ2) (IRQ4) (IRQ6) -- -- (MTU0) (MTU1) (MTU2) -- -- --
(IRQ1) (IRQ3) (IRQ5) (IRQ7) -- -- (MTU0) (MTU1) (MTU2) -- -- (SCI)
(IRQ1) (IRQ3) (IRQ5) (IRQ7) -- -- (MTU0) (MTU1) (MTU2) -- -- (SCI)
(IRQ1) (IRQ3) (IRQ5) (IRQ7) -- -- (MTU0) (MTU1) (MTU2) -- -- (SCI)
(IRQ1) (IRQ3) (IRQ5) (IRQ7) -- -- (MTU0) (MTU1) (MTU2) -- -- (SCI)
INTC
282
Table A.1
On-Chip Supporting Module Registers (cont)
Bit Names Bit 6 (A/D) (CMT0) Bit 5 (A/D) (CMT0) Bit 4 (A/D) (CMT0) Bit 3 -- (CMT1) Bit 2 -- (CMT1) -- -- -- IRQ5S -- IRQ5F -- Bit 1 -- (CMT1) -- -- -- IRQ6S -- IRQ6F -- Bit 0 -- (CMT1) -- -- NMIE IRQ7S -- IRQ7F -- -- -- -- -- PE0DR -- PE0IOR PE4MD PE0MD0 -- STR0 -- CKS0 Ch0 Common CMT PFC I/O Port E PFC I/O Port A Module INTC
Address Register H'FFFFxxxx Abbr. Bit 7 8354 8355 8356 8357 8358 8359 835A 835B 8380 8381 8384 8385 83B0 83B1 83B4 83B5 83BA 83BB 83D0 83D1 83D2 83D3 83D4 83D5 83D6 83D7 83D8 83D9 83DA 83DB 83DC 83DD CMCOR1 CMCNT1 CMCSR1 -- CMF CMCOR0 CMCNT0 CMSTR PECR2 PEIOR PEDR PAIORH PADRH ISR ICR IPRH IPRG (A/D) (CMT0)
(TIM1,2) (TIM1,2) (TIM1,2) (TIM1,2) -- -- NMIL IRQ0S -- IRQ0F -- -- -- -- -- PE7DR -- -- -- IRQ1S -- IRQ1F -- -- -- -- -- -- IRQ2S -- IRQ2F -- -- -- -- -- -- IRQ3S -- IRQ3F -- -- -- -- -- -- IRQ4S -- IRQ4F --
PA19DR PA18DR -- -- -- --
PA19IOR PA18IOR -- -- PE2DR -- PE2IOR PE5MD -- -- -- -- -- -- -- -- -- -- -- -- STR1 -- CKS1
PE14DR PE13DR PE12DR -- PE6DR PE5DR PE4DR --
PE14IOR PE13IOR PE12IOR -- PE5IOR -- -- -- -- -- -- PE4IOR PE6MD -- --
PE7IOR PE6IOR -- -- -- -- CMCSR0 -- CMF PE7MD -- -- -- -- CMIE
PE2MD0 -- -- -- -- -- -- -- -- --
-- CMIE
-- --
-- --
-- --
-- --
-- CKS1
-- CKS0
Ch1
283
Table A.1
On-Chip Supporting Module Registers (cont)
Bit Names Bit 6 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE -- -- Bit 5 AD7 -- AD7 -- AD7 -- AD7 -- ADST -- TME Bit 4 AD6 -- AD6 -- AD6 -- AD6 -- SCAN -- -- Bit 3 AD5 -- AD5 -- AD5 -- AD5 -- CKS -- -- Bit 2 AD4 -- AD4 -- AD4 -- AD4 -- CH2 -- CKS2 Bit 1 AD3 -- AD3 -- AD3 -- AD3 -- CH1 -- CKS1 Bit 0 AD2 -- AD2 -- AD2 -- AD2 -- CH0 -- CKS0 TIM1 Module A/D
Address Register H'FFFFxxxx Abbr. Bit 7 8420 8421 8422 8423 8424 8425 8426 8427 8428 8429 8610 8610 8611 8622 8623 8624 8625 862C 862D 862E 862F 8630 8631 T2COR -- T2CNT T2CSR WCR1 ADDRAH AD9 ADDRAL AD1 ADDRBH AD9 ADDRBL AD1 ADDRCH AD9 ADDRCL AD1 ADDRDH AD9 ADDRDL AD1 ADCSR ADCR T1CSR T1CNT (WR) T1CNT (RD) BCR2 IW31 CW3 -- -- -- -- -- ADF TRGE OVF
IW30 CW2 -- -- -- CMF --
IW21 CW1 W31 W11 -- CMIE --
IW20 CW0 W30 W10 -- CKS2 --
IW11 SW3 -- -- -- CKS1 --
IW10 SW2 -- -- -- CKS0 --
IW01 SW1 W21 W01 -- -- --
IW00 SW0 W20 W00 -- -- --
BSC
TIM2
--
--
--
--
--
--
--
284
Appendix B Pin States
B.1 Pin States
Pin States during Reset, and Power-Down
Pin Modes Pin Function Class Clock System control Interrupt Pin Name CK RES NMI IRQ0-IRQ7 Address bus Data bus Bus control A1-A21 D0-D15 WAIT RD CS0, CS1 CS2, CS3 WRH, WRL MTU TIOC0A, TIOC0C, TIOC1A, TIOC1B, TIOC2A, TIOC2B TxD RxD A/D converter I/O port AN0-AN6 PA18, PA19 PE0, PE2, PE4-PE7, PE12-PE14 Legend: I: Input O: Output H: High-level output L: Low-level output Z: High impedance K: Input pin with high impedance, output pin mode maintained. Reset Power-On O I I Z O Z Z H H Z H Z Power-Down Sleep O I I I O I/O I H H H H I/O
Table B.1
SCI
Z Z Z Z
O I I K
285
B.2
Bus Related Signal Pin States
Bus Related Signal Pin States
On-Chip Supporting Module Internal RAM 8-Bit Space Space H H H H H H H H H H H H H H 16-Bit Space Upper Byte H H H H H H H Lower Byte H H H H H H H Word/ Upper Longword Byte H H H H H H H Valid L H H L H H External Normal Space 16-Bit Space Lower Byte Valid L H H L H L Word/ Longword Valid L H H L H L
Table B.2
Pin Name CS0-CS3 RD R W WRH R W WRL R W A21-A1 D15-D8 D7-D0
Address Address Z Z Z Z
Address Address Address Z Z Z Z Z Z
Address Address Address Data Z Z Data Data Data
Legend: R: Read W: Write H: High-level output L: Low-level output Valid: Chip select signal corresponding with accessed area is low; chip select signal in other cases is high.
286
Appendix C Package Dimensions
Package dimensions of the SH7011 (TFP-100B) are shown in figure C.1.
Unit: mm
16.0 0.2 14 75 76 51 50
16.0 0.2
100 1 *0.22 0.05 0.20 0.04 25 0.08 M
26
0.5
*0.17 0.05 0.15 0.04
1.20 Max
1.00
1.0
1.0 0 - 8 0.5 0.1
0.10
*Dimension including the plating thickness Base material dimension
Figure C.1 Package Dimensions (TFP-100B)
0.10 0.10
287
SH7011 Hardware Manual
Publication Date: 1st Edition, December 1998 Published by: Electronic Devices Sales & Marketing Group Semiconductor & Integrated Circuits Group Hitachi, Ltd. Edited by: Technical Documentation Group UL Media Co., Ltd. Copyright (c) Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.

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